(Note that the 1.0 board requires an update to 1.1)
Board 1.0-005 is the only board that has been manufactured.
Notes dated: 18-Jun-2015 updatetd comments are in [ ].
The ECB KISS-68030 prototype board schematics are contained in this folder. This board should be considered EXPERIMENTAL at the present stage, prototype 1.0-005. The CPU board represents a direct upgrade from the Mini-M68000 board in the N8VEM ECB 100mm x 160mm format.
[update: 1.0-005 updated with 1 wire to 1.1 is the operational final board. See the update page to download the update PDF and Schematic update on p.4.]
CPU: Motorola MC68030RC-16, with provision for -20 and -25 Mhz chips. [board is stable at 25Mhz; reports received from several users that 32Mhz is operational.]
FPU: none – it just doesn't fit on this small board.
DRAM Memory: two 72-pin SIMM slots designed to hold 16Mb single sided DRAM, or 32Mb double sided DRAM. Memories are 60ns and run at 5 volts. There is provision to upgrade the memory to 64Mb single sided DRAM, or 128Mb double sided DRAM. The DRAM situation is the experimental nature of this board, since the RAS and Refresh current transients are very large (>1amp per SIMM).
SRAM Memory: 32K dip @ 35ns. To be used initially on board testing. (0xFFFE_0000..0xFFFE_FFFF) (32K maps twice to 64K interval)
ROM Memory: 512K 70ns Flash, SST (preferred) or AMD. (0xFFF0_0000..0xFFF7_FFFF) (512K Flash)
ECB Memory: this board should be able to access an ECB 4MEM board through a 256K window. (0xFFF8_0000..0xFFFB_FFFF) (256K window)
I/O Space: memory mapped. (0xFFFF_0000..0xFFFF_FFFF). (Z80 16-bit addressing)
Wait states are individually selectable for DRAM, ROM-SRAM-etc., and I/O. [DRAM-0,1,2 w.s., ROM/RAM-0,1,2 w.s., I/O-2,3,5,7 w.s.]
The required peripheral I/O board is the ECB Multifunction board, which provides the Serial I/O, NVRAM and clock, and Interrupt Controller functions, as on the Mini-M68000 board.
The DRAM controller uses GAL22V10 PLD chips to do address decoding, and directing the RAS and CAS signals to the appropriate SIMM inputs. The Refresh controller is a single 74F195A chip, which acquires the bus from the CPU, and generates the CAS-before-RAS refresh. The refresh requests are directed to the GAL's, which pass it on the all of the RAS and CAS inputs. Normal read/write RAS and CAS timing is derived from a 60+ Mhz oscillator (60-67Mhz suggested), which also generates the address multiplex signal for the three 74F257 DRAM address multiplexors. [74F257A]
The board assumes the presence of the ECB Multifunction controller to provide vectored interrupt requests. The interrupt controller on this board is an NS32202, which also provides two timers. Console I/O through a serial port is also provided by this board.