Table of Contents
The CPU280 is a single-board ECB-interface computer based on the Z280 microprocessor from Zilog, designed and originally manufactured by Tilmann Reh in the early 1990's. The CPU280 runs the Z280 in the Z-BUS mode with a 16-bit data bus. 512KB, 1MB, 2MB, or 4MB of dynamic RAM can be installed. The system boots to CP/M+ from EPROM. The CPU280 was one of the very few hobbyist-buildable Z280 CP/M computers ever made. RBC forum member fritzeflink maintains an archive of information about the CPU280 at his site http://oldcomputers.dyndns.org/public/pub/rechner/zilog/z280/index.html.
Late in 2016, RBC forum member lowen contacted Tilmann Reh and obtained permission to have a new run of boards made. Tilmann very graciously provided the manufacturing files as well as all necessary documentation and source code to rebuild the system, and lowen was able to get a beta run of ten boards made and distributed to several beta builders. RBC forum member Wayne W developed a build setup to rebuild the EPROM images and floppy disk images and set up a github at https://github.com/wwarthen/CPU280 for distribution and development. Several boards were successfully constructed using the beta run, and lowen had another ten boards fabricated. In spring 2018, another ten boards were run.
Tilmann Reh has given blanket permission for unmodified redistribution of the CPU280 files. Tilmann requests notification if the design is modified. Quoting his emailed permission, received by Lowen on 1/10/2017:
For me it's OK to distribute all of the CPU280 stuff (including the gerber files, the PDFs and the software) freely - as long as the design is not modified without my expressed permission.
The original design files in Eagle .BRD format (CPU280-EAGLE.zip ) are available as well. Here is what Tilmann has to say about the way Eagle was used in the early 1990s:
Take care that in the 90s, there was no schematic editor in EAGLE. Instead, i just drew the schematic with the board editor. So now you need to edit both files to keep them synced. (I include the “schematic” file so you can update your documentation/PDF according to the patched PCB.)
So the schematic is also a .BRD file and was drawn in the layout editor of Eagle.
Board and Schematic: :boards:sbc:cpu280:cpu280_hardware-manual_en.pdf
Manufacturing Files: :boards:sbc:cpu280:z280-e5-gerber.zip
KiCAD Files: Tilmann's original Eagle .BRD files are: :boards:sbc:cpu280:cpu280-eagle.zip Translation to KiCAD is not planned at this time; volunteers to do this are welcome!
<Include thinks like parts lists, BOMs, test software, notes from the board designer, etc in this section.>
Please use this space to add any notes/comments on this board that don't fit into the above sections. (Periodically, these comments may be re-arranged to be better incorporated into a new revision of the wiki page.) Please sign your comments using the wiki “Insert Signature” feature! — Andrew Bingham 2016/02/27 13:01
Notes from Richard Edwards
The following are notes from my build — Richard Edwards 2019/08/10 16:32—
The first LED goes off after reset
Middle LED stays lit if the battery in the DS1287/DS1287A is flat otherwise it goes out.
You can fix a flat battery in a DS1287 using a technique like the following https://youtu.be/NdlSfqto_0o Although it looks drastic IMHO you have nothing to lose by doing this modification to make the chip usable again.
LED closest to the CPU stays on while the memory test is occurring. Once it goes off the memory test is completed.
Best suggestion is to build new ROM's from the source per the link up the page. However if you need you can also use the v1.20.3 zip in the files section. Note I suspect that if you have version 1.20.1 ROM's then your board will not be showing anything on the serial console. I had the same issue and read in the very long forum thread about the CPU280 that someone worked out that the board was trying to display console on a graphics adapter that doesn't exist.
I had issues with the ANSICON in the git respositry so I downloaded the latest from here http://adoxa.altervista.org/ansicon/
Take a look at the PDF and make sure that you have BCE in the right location. Sometimes the board silk screen may not match the transistor pin out. If you look at some of the uploaded photos you can see the differences in peoples builds.
The following cable worked for me. You then connect the CPU280 to a terminal via a null modem cable.
|CPU280 Board||DB9 PIN Male|
|1 - GND||5|
|3 - TXD||3|
|5 - RXD||2|
|7 - RTS||7|
|9 - CTS||8|
I always find this link useful to work out what serial pin does what https://en.wikipedia.org/wiki/Serial_port
I found the Jumpers zip file in the forum threads and have uploaded it here. Gives a very good description of what each one does.
Note: If you bridge Jumper 7 then it will force the CPU280 into setup mode.
I connected a PC 3.5“ FDD to the CPU280 using a straight through cable.
Drive B: is the first connector
Drive A: is the second connector
in the CPU280 Setup I used the following configuration
A: 3.5” HD, 80 tracks, double-sided
B: 3.5“ HD, 80 tracks, double-sided
Sample Configuration Options (J7 Jumpered)
CPU280 Boot Loader V1.2 RBC 8-Mar-2017
based on Cold Loader Program V1.13 TR 950314
Press DEL to run SETUP.
2048k RAM ok
1. Disk Drives
0. Exit (Reboot)
actual values:\\ A: 5.25" DD, 80 tracks, double-sided\\ B: 5.25" DD, 80 tracks, double-sided\\ C: ---\\ D: ---
1. Drive A: 2. Drive B: 3. Drive C: 4. Drive D: 0. \back --> \1 0. no \drive 1. 3.5" \DD 2. 3.5" \HD 3. 8" 4. 5.25" HD \360 5. 5.25" \DD 6. 5.25" HD 300/\360 --> \2 0. 40 \tracks 1. 80 \tracks --> \1 0. single \sided 1. double \sided --> 1
actual values: A: 3.5" HD, 80 tracks, double-\sided B: 5.25" DD, 80 tracks, double-\sided C: --- D: ---
1. Drive A: 2. Drive B: 3. Drive C: 4. Drive D: 0. \back --> \2 0. no \drive 1. 3.5" \DD 2. 3.5" \HD 3. 8" 4. 5.25" HD \360 5. 5.25" \DD 6. 5.25" HD 300/\360 --> \2 0. 40 \tracks 1. 80 \tracks --> \1 0. single \sided 1. double \sided --> 1
actual values: A: 3.5" HD, 80 tracks, double-\sided B: 3.5" HD, 80 tracks, double-\sided C: --- D: ---
1. Drive A: 2. Drive B: 3. Drive C: 4. Drive D: 0. \back --> 0
1. Disk \Drives 2. \Interfaces 3. \Other 0. Exit (Reboot) –> 3
actual values: Memory 0k, Daylight Saving disabled, Boot A:, Chain *
1. Memory \Size 2. Daylight \Saving 3. Boot \Drive 4. Drive Search \Chain 0. \back --> \1 Memory: 0=512k, 1=1M, 2=2M, 3=4M --> 3
actual values: Memory 4096k, Daylight Saving disabled, Boot A:, Chain *
1. Memory \Size 2. Daylight \Saving 3. Boot \Drive 4. Drive Search \Chain 0. \back --> \3 Boot Drive: A..P (Q=EPROM) --> Q
actual values: Memory 4096k, Daylight Saving disabled, Boot Q:, Chain *
1. Memory \Size 2. Daylight \Saving 3. Boot \Drive 4. Drive Search \Chain 0. \back --> 0
1. Disk \Drives 2. \Interfaces 3. \Other 0. Exit (Reboot) Sample Boot Output
This is what I get on the console when it boots. I used setup to set my boot drive to Q which is the EPROM.
CPU280 Boot Loader V1.2 RBC 8-Mar-\2017 http://www.retrobrewcomputers.org based on Cold Loader Program V1.13 TR \950314 Press DEL to run SETUP. 2048k RAM ok
CP/M-3 Loader V1.2 RBC 8-Mar-\2017 based on CP/M-3 Loader V1.\13 Booting system file from EPROM
BNKBIOS3 SPR FE00 \0200 BNKBIOS3 SPR D000 \2000 RESBDOS3 SPR F800 \0600 BNKBDOS3 SPR A200 2E00
CP/M-3 BIOS V1.2 RBC 8-Mar-\2017 http://www.retrobrewcomputers.org based on CP/M-3 BIOS V1.13 TR 950314
E: MDrive 3840k
happy building — Richard Edwards 2019/08/10 16:40—
Notes from Will Sowerbutts
Reh CPU-280 Board:
- I fitted a pair of W27C512 EEPROMs instead of UV EPROMs, they can be quickly programmed with the common MiniPro TL866 programmers.
- From reading the BOM, I was confused which two of the CK1-CK27 caps were the 10uF tantalums. They are CK1 and CK9.
- You need to fit an insulator under the crystals in order to prevent them shorting out on PCB vias. I 3D printed a small shim to do the job.
- The manual says that J5 (EEPROM type select) is pre-connected to suit 27C256 ROMs. This was not the case on my PCB. A 3-pin header and jumper is required at J5.
- CN3 is a 20-pin connector with two RS232 ports on it. One might think you can just split the 20-way ribbon cable and connect each 10-pin strip to an IDC DB9, however this will not work as the pinout is wrong. You have to use the pin mapping that Richard describes above.
- The 9.6MHz oscillator at Q3 is not required if you're using only standard PC 3.5” floppy drives.
- I found 15ns ATF16V8B PLDs worked well in my CPU-280.
- See the note below about using 74LS parts for IC6, IC7 and IC8.
- The CPU-280 manual says to measure the CAS pulse width and adjust the value of C6 to get the CAS pulse width to 20ns. Page 22 of this document shows a timing diagram. You need to inspect the width of the positive pulses on one of the /CAS lines during a burst memory access, as shown in the third diagram, “Burst-Speicherzugriffe (RAM)”. To test this I probed pin 17 on the Z280CAS4 GAL (/CAS for DRAM ICs 11 and 12) while MBASIC.COM ran an infinite loop (something to keep the CPU busy that wouldn't fit in cache).
Reh ECB-IDE Board:
- Watch out for the orientation of RN4, RN5, RN6 – Pin 1 is not in the same orientation on each network.
- There isn't enough space around D2, D3, D4, D5 to fit them all even using 3mm LEDs. I don't use -5V, -12V or +12V so I fitted only D3 (+5V) and D1 (IDE activity).
- To set up the active terminator, you need to adjust P1 until you get around 2.7V on pin 1 of the bus termination resistor networks (RN4, RN5, RN6).
- You do not need to fit R6, R7, R8, R9 if you are using this board with CPU-280.
- See the note below about using 74LS parts for IC2 and IC3.
- You need to fit a jumper across pins 1-2 (pins closest to parallel port connector) on SW1 and SW2 otherwise /RESET or /NMI will be constantly asserted.
- You also need a jumper at J1 to select the reset style (if using with CPU-280, jumper the two pins closest to the centre of the board).
I found that the ECB-IDE board used with CPU-280 would give occasional but reproducible disk errors when reading from the IDE drive (using a Compact Flash card). Changing to a different CF card made no difference.
The issue went away when the 74ACT245 at either REH-IDE IC3 or CPU-280 IC7 (or both) were substituted with 74LS245 or 74AHCT245 (other logic families may also work, these are the two I tested with successfully).
74LS244 and 74LS245 have hysteresis at the bus inputs to improve noise margins. I have therefore installed 74LS on all bus transceivers:
- CPU-280 IC6, IC8 and REH-IDE IC2 are substituted with 74LS244
- CPU-280 IC7 and REH-IDE IC3 are substituted with 74LS245
Connecting PC floppy drives:
To connect PC floppy drives to the CPU-280, I soldered a shrouded 34-pin header to the last 34 pins of CN2, pins 17-50. These are the 34 pins closest to the RTC chip, and pin 1 on the header should be pin 17 on CN2. The pinout is not directly compatible with PC floppy drives, so I made up an adapter board to convert this to a standard PC floppy cable. The adapter has two 34-pin headers: An input which connects to the CPU-280 with a straight through cable, and an output which connects to a standard PC floppy cable with two drives which the CPU-280 sees as A: (before the twist) and B: (after the twist). On the output header I removed pin 3, which was blocked as a keying pin on several of the standard PC floppy cables I have.
|CPU-280 CN2 pin||Adapter 34-pin input||Adapter 34-pin output||Signal Name|
|1-16||n/c||n/c||No Connect - Unused pins on CN2|
|32||16||10 and 16||MOTOR ON|
|17-49 (All odd pins)||1-33 (All odd pins)||1-33 (All odd pins)||GROUND|
— Will Sowerbutts 2021/03/14 21:11—
|2n3904.pdf||166.8 KiB||2019/08/10 02:27|
|cpu280-1.20.3.zip||1.5 MiB||2019/08/10 02:28|
|cpu280-burstmode-cas.jpg||2.2 MiB||2021/03/14 17:11|
|cpu280-eagle.zip||61.9 KiB||2018/06/26 09:00|
|cpu280-v1.20.1.zip||684.0 KiB||2017/05/26 14:21|
|cpu280-v1.20.2.zip||1.4 MiB||2017/08/01 00:22|
|cpu280_hardware-manual_en.pdf||595.2 KiB||2017/05/26 13:34|
|cpu280_software-manual_en.pdf||395.4 KiB||2017/05/26 13:34|
|jcoffman-1.jpg||149.1 KiB||2017/05/26 14:23|
|jcoffman-2.jpg||189.8 KiB||2017/05/26 14:23|
|lro-board-201612-1.jpg||6.0 MiB||2017/05/26 14:23|
|reh-cpu280-lro-2016-1.jpg||4.9 MiB||2017/05/26 14:23|
|reh-cpu280-lro-2016-web.jpg||106.2 KiB||2017/05/26 14:17|
|wayne-w-1.jpg||1.8 MiB||2017/05/26 14:23|
|z280-e5-gerber.zip||55.0 KiB||2017/05/26 13:33|
|z280_jumper_information.zip||1.5 MiB||2019/08/10 02:27|
|z280_reh.pdf||1.4 MiB||2017/07/05 15:38|