The MiniMax8085 project has been brewing for almost three years. Sometime in the spring of 2014 my kids and I visited local the surplus store, where my kids found some Intel 8000 series parts in the kids-fill-your-bucket area. Among these ICs were there: an 8085 CPU, an 8155 RAM with I/O ports and timer, a couple of 8255 PPIs, an 8282 latch, and some 27C128 UV EPROMs. It looked like a good start for an 8085 based computer that can be used to teach my kids some computer design and programming basics.
I wanted the project to be simple to build, with a minimal number of components, but yet to be a fully functional single board computer (e.g. to include the memory and an input/output device, for example a UART) with an extension bus. I checked the Internet for existing homebrew 8085 computers and found Roman Fülek's NCB85 and NCB85v2 projects, and Glitch Works 8085 projects. While I liked these projects, they didn't quite meet my project design goals:

• NCB85 was the closest, but it doesn't have an extension bus
• NCB85v2 is a little bit too complicated for my needs
• Glitch Works 8085 project didn't have an on-board UART

The resulting design includes 8085 CPU, 8251 USART, 32 KiB SRAM, 32 KiB or 16 KiB ROM. It uses a GAL16V8/ATF16V8 simple programmable logic device (SPLD) instead of discrete logic ICs for the address decode and the frequency divider for USART. It reduces the number of components, allows for tweaking the configuration by re-programming the SPLD, and provides an introduction to the programmable logic devices.

• 80C85A or 8085A CPU, 3.072 MHz or 4.9152 MHz CPU clock frequency
• 82C51A or 8251A USART for console connection
• 32 KiB of battery backed SRAM
• Up to 32 KiB of ROM. EEPROM, UV EPROM or Flash ROM memory is supported
• 40-pin extension bus connector, including most of 8085 signals and demultiplexed data and address buses

Mini8085 - KiCad - 1.0.zip - KiCad schematic and PCB layout files
Mini8085 - Schematic - 1.0.pdf - Schematic in PDF format
Mini8085 - Board - 1.0.pdf - PCB layout in PDF format

The MiniMax8085 is based on the Intel 8085A CPU (U1). The 74*573 octal latch (U6) is used to demultiplex the lower 8-bit of address and data bus.
The board uses the Intel 8251A USART (U2) for serial input / output, for example for connecting a console. The MAX232A RS-232 driver/receiver (U7) is used to convert TTL logic levels to RS-232 voltage.
The 62256 32 KiB SRAM (U4) is used for the system RAM. The RAM is battery backed using the DS1210 NVRAM controller (U8).
The board supports a variety of ROM options (U3): The 28C256 EEPROM; UV EPROMs, such as 27C256 (32 KiB), 27C128 (16 KiB), and 27C64 (8 KiB); or The 29C256 Flash ROM ICs. Normally the ROM is mapped to the CPU memory beginning from the address 0x0000, while the RAM is mapped beginning from the address 0x8000. The ROM and RAM addresses can be swapped by pulling /SWAP_MEM signal low. This can be used, for example, to implement a CP/M extension card.
The GAL16V8 simple programmable logic device (U5) implements all the required “glue” logic functions:

• Address decode and chip select for the USART. The default USART I/O address is 0x08.
• Clock divider that divides the CPU clock to obtain USART transmit and receive clock. The divisor value depends on the CPU speed. Fuse maps with divide by 10 and 20, divide by 13 and 26, and divide by 16 and 32 ratios are provided to support common 8085A CPU clocks: 3.072 MHz, 4 MHz, 4.9152 MHz, 6.144 MHz, and 8 MHz.
• Address decode and chip select for the ROM and SRAM. The address decode logic include additional /SWAP_MEM input, which by default is configured to swap address mapping of ROM and RAM.

Please refer to the Simple Programmable Logic Device section below for more details regarding the SPLD configuration and programming.
The MiniMax8085 includes a 40-pin extension connector (P4), that features the 8085A address and data buses, and control signals. Please refer to the Jumpers and Connectors section below for the connector pinout and signals description.

These jumpers configure how pins 1 and 27 of the ROM IC (U3) are connected. The jumper settings are printed on the bottom side of the PCB.

JP3 sets the USART input clock frequency

Connect regulated +5V power supply to this connector.

P2 exposes the 8085A CPU serial input and output lines.

P3 is the serial port connector. It is normally used for connecting a console or terminal. P3 uses pinout similar to that of IBM AT serial port (with some signals missing). Use a null modem cable to connect to a PC.

P4 exposes the 8085A CPU address and data buses, and control signals.

Connector P5 -VBAT

P5 is used to connect the battery for the SRAM backup. A 3-volt lithium cell, or 2-3 alkaline batteries connected in series can be used for this purpose.

As described above, the MiniMax8085 SBC uses a GAL16V8 simple programmable logic device (SPLD) to implement all the necessary glue logic. The SLPD images are available in Mini8085-SPLD-1.2.zip file in the downloads section below. Here are some files contained in that ZIP archive:
Mini8085-3.072MHz.pld - SPLD source code for a system with CPU running on 3.072 MHz or 6.144 MHz* clock frequency
Mini8085-3.9936MHz.pld - SPLD source code for a system with CPU running on 3.9936 MHz (4 MHz) or 8 MHz clock frequency
Mini8085-4.9152MHz.pld - SPLD source code for a system with CPU running on 4.9152 MHz clock frequency
Mini8085-3.072MHz.jed - SPLD fuse map for a system with CPU running on 3.072 MHz or 6.144 MHz* clock frequency
Mini8085-3.9936MHz.jed - SPLD fuse map for a system with CPU running on 3.9936 MHz (4 MHz) or 8 MHz clock frequency
Mini8085-4.9152MHz.jed - SPLD fuse map for a system with CPU running on 3.072 MHz clock frequency
* When used with 6.144 MHz or 8 MHz CPU clock frequency, the USART clock will be doubled. So that it will work on 19200 bps instead of 9600 bps, or 38400 bps instead of 19200 bps.

The SPLD IC has to be programmed using an EPROM programmer, such as a popular MiniPro TL866CS programmer. The process is very similar to programming regular EPROM ICs:

• Select IC manufacturer: Lattice for GAL16V8 or Atmel for ATF16V8)
• Select the SPLD type: GAL16V8 or ATF16V8
• Load the SPLD fuse map - pick either Mini8085-3.072MHz.jed or Mini8085-4.9152MHz.jed file, depending on the CPU frequency (or the crystal resonator you are using).
• Program the SPLD. You might want to disable “lock” option, so that SPLD will remain readable after the programming.

The Mini8085-3.072MHz.pld and Mini8085-4.9152MHz.pld files contain the SPLD source code, that describes the logic equations defining the desired SPLD functionality. The source code can be divided into the following sections:

This part contains the name of the SPLD and the project name:

GAL16V8       ; 8085 SBC Logic first line : used GAL
8085Mini      ;                second line: any text (max. 8 char.)

This part assigns names to the SPLD pins. The names order corresponds to the pin numbers: the first line assigns names to the pins 1 - 10, and the second line to the pins 11 - 20. Note that several pins have fixed functions: pin 1 - Clock, pin 10 - GND, pin 11 - /OE, and pin 20 - VCC. Also pins 2 - 9 can be used as inputs only, while pins 12 - 19 can be used as either inputs or outputs.

Clock IOM    A15    SWAPMEM A7    A6    A5    A4    A3   GND
/OE   RAMCS  ROMCS  USARTCS Q4    Q3    Q2    Q1    Q0   VCC

The frequency divider is implemented as a synchronous counter, where all the outputs change their state simultaneously with the rising edge of the Clock signal. To achieve this, the SPLD is configured in registered mode (this is done automatically, by the SPLD assembler). In this mode the SPLD outputs with .R suffix (Q0.R - Q4.R) are configured as D flip-flops, and their logic equations describe the next state of the flip-flops (the values on their D inputs, that will be latched with the Clock signal). For example, in the Mini8085-4.9152MHz.pld the next state of Q0 output is defined to be the inverse of its current state: Q0.R = /Q0. The Q0 - Q2 outputs are the outputs of intermediate stages of counter/divider, and they are not used in the MiniMax8085. The USART clock inputs are connected to either Q3 or Q4 output, depending on the position of the jumper JP3, resulting in either divide by 10 or 20 for 3.072 MHz CPU clock (using the Mini8085-3.072MHz.pld fuse map) or in divide by either 16 or 32 for 4.9152 MHz CPU clock (using the Mini8085-4.9152MHz.pld fuse map).

Mini8085-4.9152MHz.pld: 5-bit binary counter, or divide by 32 frequency divider.

Q0.R =   /Q0

Q1.R =    Q1 * /Q0
       + /Q1 *  Q0

Q2.R =    Q2 * /Q1
       +  Q2 * /Q0
       + /Q2 *  Q1 *  Q0

Q3.R =    Q3 * /Q2
       +  Q3 * /Q1
       +  Q3 * /Q0
       + /Q3 *  Q2 *  Q1 *  Q0

Q4.R =    Q4 * /Q3
       +  Q4 * /Q2
       +  Q4 * /Q1
       +  Q4 * /Q0
       + /Q4 *  Q3 *  Q2 *  Q1 *  Q0

Mini8085-3.072MHz.pld: Q2-Q0 implement divide by 5 frequency divider, Q3 and Q4 stages divide the frequency further by 2 and 4 respectively.

Q0.R =   /Q2 * /Q0

Q1.R =   /Q2 * /Q1 *  Q0
       + /Q2 *  Q1 * /Q0

Q2.R =   /Q2 *  Q1 *  Q0

Q3.R =    Q3 * /Q2
       + /Q3 *  Q2

Q4.R =    Q4 * /Q3
       +  Q4 * /Q2
       + /Q4 *  Q3 *  Q2

These equations activate /ROMCS and /RAMCS signals:
The /ROMCS is active (LOW) when 8085 IO/M signal is LOW, indicating a memory access, and either A15 is LOW (lower 32 KiB of memory address space) and SWAPMEM is inactive (HIGH), or then A15 is HIGH (upper 32 KiB of memory address space), and SWAPMEM is active (LOW).
The /RAMCS is active (LOW) when 8085 IO/M is LOW, indicating a memory access, and either A15 is HIGH (upper 32 KiB of memory address space) and SWAPMEM is inactive (HIGH), or then A15 is LOW (lower 32 KiB of memory address space), and SWAPMEM is active (LOW).

/ROMCS =   /IOM *  SWAPMEM * /A15
         + /IOM * /SWAPMEM *  A15

/RAMCS =   /IOM *  SWAPMEM *  A15
         + /IOM * /SWAPMEM * /A15

This equation activates the /USARTCS signal. It is active (LOW) when 8085 IO/M signal is HIGH, indicating an I/O port access, address lines A7-A4 are LOW, and address line A3 is high. So that USART is selected using 00001xxxb addresses (8h-0Fh).

/USARTCS = IOM * /A7 * /A6 * /A5 * /A4 * A3

Link to the project on Mouser.com - View and order all components except of the 8085A CPU, the 8251A USART, and the PCB.
Link to the project on OSHPark.com - View and order the MiniMax8085 PCB.

• CMOS parts are preferred for lower power consumption.
  • 80C85 (CPU) - Any type in DIP-40 package will do. Use 6.144 MHz crystal for 3 MHz parts. Such parts usually don't have any numeric suffix in the part name. For example Intel P8085AH is a 3 MHz part, while Intel P8085AH-2 is a 5 MHz part.
  • CMOS parts: MSM80C85A or M80C85A (OKI), CA80C85B (Calmos, Tundra), IM1821VM85A (Soviet/Russian Clone)
  • NMOS parts: P8085A (Intel, AMD), P8085AH, P8085AH-2, P8085AH-1 (Intel, newer HMOS process, 3 MHz, 5 MHz, and 6 MHz parts respectively), M5L8085AP (Mitsubishi), TMP8085AP (Toshiba), and so on.
• 80C51A (USART) - Any type in DIP-28 package.
• 28C256 (EEPROM, EPROM) - The board support a wide variety of ROMs. Note that JP1 and JP2 jumpers need to be set according to the ROM type.
  • 28C256 EEPROM: Atmel/Microchip AT28C256, Xicor X28C256
  • CMOS UV EPROMs: 27C256 UV EPROMs (32 KiB), 27C128 UV EPROMs (16 KiB), 27C64 UV EPROMs (8 KiB)
  • NMOS UV EPROMs: 27256 UV EPROMs (32 KiB), 27128 UV EPROMs (16 KiB), 2764 UV EPROMs (8 KiB)
  • 62256-like NVRAM (32 KiB)
  • AT29C256 Flash ROM
• 62256 (SRAM) - A low-power CMOS SRAM 32KiB, in DIP-28 wide (600 mils) packages. Here are some common parts:
  • In production: AS6C62256 (Alliance Memory), CY62256N (Cypress)
  • Old stock: HM62256LP (Hitachi), HY62256 (Hyundai), KM62256 (Samsung), UM62256 (UMC)
• GAL16V8 (SPLD): Needs to be in DIP-20 package
  • In production: Atmel/Microchip ATF16V8
  • Old stock: Lattice GAL16V8 (any modification)
  • iCT PEEL16V8 might work, but it is not supported by common MiniPro TL866CS programmer
• 74HC573 (Octal D Latch with 3-STATE Outputs) - Can be replaced with any 74-series family that works with 5V power supply voltage.
  • CMOS parts: 74HC573, 74ACT573, 74HCT573, 74AHCT573, 74AC573, 74ACT573
  • TTL parts: 74ALS573, 74F573, 74LS573
• MAX232A (RS-232 Drivers/Receivers) - There is a variety of compatible ICs available from various manufacturers. Note that the original MAX232 part as well as some compatible ICs require 1 uF capacitors for charge pumps (C7-C11).
  • Maxim: MAX232A, MAX202, MAX232
  • Texas Instruments: TRS202, MAX232
  • Exar: SP232
  • Analog Devices: ADM202, ADM232
  • Intersil: HIN202, HIN232
• LED D2 - Can be replaced by a 3 mm LED with pins bent at 90 degrees.

MiniMax8085 uses MON85 Software Debug Monitor For the 8085/8080 written by Dave Dunfield. Specifically it was tested with the improved by Roman Borik version 1.2: mon85-v12-mini85.zip. This version adds support for undocumented 8085 instructions and flags.

The famous Tiny BASIC 2.0 written by Li-Chen Wang and modified by Roger Rauskolb, runs on MiniMax8085 with very little modifications: The 8251 USART I/O address needs to be updated, and its initialization parameters need to be slightly updated - to use 1 stop bit instead of two, and to enable CTS/RTS flow control. Also the RAM addresses need to be updated to start from 8000h.
For your enjoyment the original Tiny BASIC article from the December 1976 issue of Interface Age magazine - TinyBASIC-2.0.pdf, the source files and the ROM image - tinybasic-2.0-mini85.zip, are provided.

• Q: Board doesn't work. No output on the serial console.
• A1: Make sure that the ROM type is configured properly using JP1 and JP2 jumpers.
• A2: The firmware configures USART with RTS/CTS flow control enabled. Check that your terminal emulation software has RTC/CTS flow control enabled, and that you're using a null-modem cable with RTS and CTS signals on one side connected to CTS and RTS signals on the other side. Alternatively you can connect pin 7 (RTS) and pin 8 (CTS) on the P3 connector, and use a three wire serial cable with TX, RX, GND signals only.
• Q: Board works unreliably, gets randomly stuck when board is touched, requires reset every so often.
• A: Assuming that DS1210 is installed, make sure you have 3V-4.5V battery connected to connector P5 (observe polarity). Alternatively you can put a jumper across P5, or remove DS1210 and install jumpers instead as indicated on the PCB.

• Roman Fülek's NCB85:
  • GitHub: https://github.com/ncb85/
  • Roman's NCB85 page: http://archeocomp.blogspot.com/2013/01/ncb85.html
  • Martin's page: http://www.8bity.cz/2011/ncb85-single-board-computer/
  • Write-up: http://www.nostalcomp.cz/ncb85.php
  • Roman's NCB85v2 page: http://archeocomp.blogspot.com/2014/01/ncb85-7-nove-ncb85v2.html
  • MON85 updated by Roman Borik: http://blog.borik.net/2012/01/upraveny-monitor-pre-ncb85.html
• Glitch Works 8085 SBC
  • 8085 Microprocessor Projects: http://www.glitchwrks.com/8085projects.html
  • GitHub: https://github.com/glitchwrks/8085_sbc
• Coffee, bits and bikes
  • Mini85v2: http://bitsnbikes.blogspot.sk/2012/02/mini85.html
• Ken Shirriff's Blog - 8085 Reverse Engineering:
  • Inside the ALU of the 8085 microprocessor: http://www.righto.com/2013/01/inside-alu-of-8085-microprocessor.html
  • Notes on the PLA on the 8085 chip: http://www.righto.com/2013/01/notes-on-pla-on-8085-chip.html
  • 8085 instruction set: the octal table: http://www.righto.com/2013/02/8085-instruction-set-octal-table.html
  • Silicon reverse engineering: The 8085's undocumented flags: http://www.righto.com/2013/02/looking-at-silicon-to-understanding.html
  • The 8085's register file reverse engineered: http://www.righto.com/2013/03/register-file-8085.html
  • Reverse-engineering the 8085's ALU and its hidden registers: http://www.righto.com/2013/07/reverse-engineering-8085s-alu-and-its.html
  • Reverse-engineering the flag circuits in the 8085 processor: http://www.righto.com/2013/07/reverse-engineering-flag-circuits-in.html
  • Reverse-engineering the 8085's decimal adjust circuitry: http://www.righto.com/2013/08/reverse-engineering-8085s-decimal.html
• 8080 Opcodes: http://pastraiser.com/cpu/i8080/i8080_opcodes.html
• The Macroassembler AS - A macroassembler supporting Intel 8085: http://john.ccac.rwth-aachen.de:8000/as/
• GALasm 2.1 - Portable GAL Assembler: https://github.com/daveho/GALasm