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The MiniMax8085 project has been brewing for almost three years. Sometime in the spring of 2014 my kids and I visited local the surplus store, where my kids found some Intel 8000 series parts in the kids-fill-your-bucket area. Among these ICs were there: an 8085 CPU, an 8155 RAM with I/O ports and timer, a couple of 8255 PPIs, an 8282 latch, and some 27C128 UV EPROMs. It looked like a good start for an 8085 based computer that can be used to teach my kids some computer design and programming basics.
I wanted the project to be simple to build, with a minimal number of components, but yet to be a fully functional single board computer (e.g. to include the memory and an input/output device, for example a UART) with an extension bus. I checked the Internet for existing homebrew 8085 computers and found Roman Fülek's NCB85 and NCB85v2 projects, and Glitch Works 8085 projects. While I liked these projects, they didn't quite meet my project design goals:
The resulting design includes 8085 CPU, 8251 USART, 32 KiB SRAM, 32 KiB or 16 KiB ROM. It uses a GAL16V8/ATF16V8 simple programmable logic device (SPLD) instead of discrete logic ICs for the address decode and the frequency divider for USART. It reduces the number of components, allows for tweaking the configuration by re-programming the SPLD, and provides an introduction to the programmable logic devices.
Mini8085 - KiCad - 1.0.zip - KiCad schematic and PCB layout files
Mini8085 - Schematic - 1.0.pdf - Schematic in PDF format
Mini8085 - Board - 1.0.pdf - PCB layout in PDF format
The MiniMax8085 is based on the Intel 8085A CPU (U1). The 74*573 octal latch (U6) is used to demultiplex the lower 8-bit of address and data bus.
The board uses the Intel 8251A USART (U2) for serial input / output, for example for connecting a console. The MAX232A RS-232 driver/receiver (U7) is used to convert TTL logic levels to RS-232 voltage.
The 62256 32 KiB SRAM (U4) is used for the system RAM. The RAM is battery backed using the DS1210 NVRAM controller (U8).
The board supports a variety of ROM options (U3): The 28C256 EEPROM; UV EPROMs, such as 27C256 (32 KiB), 27C128 (16 KiB), and 27C64 (8 KiB); or The 29C256 Flash ROM ICs. Normally the ROM is mapped to the CPU memory beginning from the address 0x0000, while the RAM is mapped beginning from the address 0x8000. The ROM and RAM addresses can be swapped by pulling /SWAP_MEM signal low. This can be used, for example, to implement a CP/M extension card.
The GAL16V8 simple programmable logic device (U5) implements all the required "glue" logic functions:
Please refer to the Simple Programmable Logic Device section below for more details regarding the SPLD configuration and programming.
The MiniMax8085 includes a 40-pin extension connector (P4), that features the 8085A address and data buses, and control signals. Please refer to the Jumpers and Connectors section below for the connector pinout and signals description.
These jumpers configure how pins 1 and 27 of the ROM IC (U3) are connected. The jumper settings are printed on the bottom side of the PCB.
JP3 sets the USART input clock frequency
Connect regulated +5V power supply to this connector.
P2 exposes the 8085A CPU serial input and output lines.
P3 is the serial port connector. It is normally used for connecting a console or terminal. P3 uses pinout similar to that of IBM AT serial port (with some signals missing). Use a null modem cable to connect to a PC.
P4 exposes the 8085A CPU address and data buses, and control signals.
<font inherit/inherit;;inherit;;inherit font-weight: bold;>Connector P5 -</font>VBAT
P5 is used to connect the battery for the SRAM backup. A 3-volt lithium cell, or 2-3 alkaline batteries connected in series can be used for this purpose.
As described above, the MiniMax8085 SBC uses a GAL16V8 simple programmable logic device (SPLD) to implement all the necessary glue logic. The SLPD images are available in Mini8085-SPLD-1.2.zip file in the downloads section below. Here are some files contained in that ZIP archive:
Mini8085-3.072MHz.pld - SPLD source code for a system with CPU running on 3.072 MHz or 6.144 MHz* clock frequency
Mini8085-3.9936MHz.pld - SPLD source code for a system with CPU running on 3.9936 MHz (4 MHz) or 8 MHz clock frequency
Mini8085-4.9152MHz.pld - SPLD source code for a system with CPU running on 4.9152 MHz clock frequency
Mini8085-3.072MHz.jed - SPLD fuse map for a system with CPU running on 3.072 MHz or 6.144 MHz* clock frequency
Mini8085-3.9936MHz.jed - SPLD fuse map for a system with CPU running on 3.9936 MHz (4 MHz) or 8 MHz clock frequency
Mini8085-4.9152MHz.jed - SPLD fuse map for a system with CPU running on 3.072 MHz clock frequency
* When used with 6.144 MHz or 8 MHz CPU clock frequency, the USART clock will be doubled. So that it will work on 19200 bps instead of 9600 bps, or 38400 bps instead of 19200 bps.
The SPLD IC has to be programmed using an EPROM programmer, such as a popular MiniPro TL866CS programmer. The process is very similar to programming regular EPROM ICs:
The Mini8085-3.072MHz.pld and Mini8085-4.9152MHz.pld files contain the SPLD source code, that describes the logic equations defining the desired SPLD functionality. The source code can be divided into the following sections:
This part contains the name of the SPLD and the project name:
GAL16V8 ; 8085 SBC Logic first line : used GAL
8085Mini ; second line: any text (max. 8 char.)
This part assigns names to the SPLD pins. The names order corresponds to the pin numbers: the first line assigns names to the pins 1 - 10, and the second line to the pins 11 - 20. Note that several pins have fixed functions: pin 1 - Clock, pin 10 - GND, pin 11 - /OE, and pin 20 - VCC. Also pins 2 - 9 can be used as inputs only, while pins 12 - 19 can be used as either inputs or outputs.
Clock IOM A15 SWAPMEM A7 A6 A5 A4 A3 GND
/OE RAMCS ROMCS USARTCS Q4 Q3 Q2 Q1 Q0 VCC
The frequency divider is implemented as a synchronous counter, where all the outputs change their state simultaneously with the rising edge of the Clock signal. To achieve this, the SPLD is configured in registered mode (this is done automatically, by the SPLD assembler). In this mode the SPLD outputs with .R suffix (Q0.R - Q4.R) are configured as D flip-flops, and their logic equations describe the next state of the flip-flops (the values on their D inputs, that will be latched with the Clock signal). For example, in the Mini8085-4.9152MHz.pld the next state of Q0 output is defined to be the inverse of its current state: Q0.R = /Q0. The Q0 - Q2 outputs are the outputs of intermediate stages of counter/divider, and they are not used in the MiniMax8085. The USART clock inputs are connected to either Q3 or Q4 output, depending on the position of the jumper JP3, resulting in either divide by 10 or 20 for 3.072 MHz CPU clock (using the Mini8085-3.072MHz.pld fuse map) or in divide by either 16 or 32 for 4.9152 MHz CPU clock (using the Mini8085-4.9152MHz.pld fuse map).
Mini8085-4.9152MHz.pld: 5-bit binary counter, or divide by 32 frequency divider.
Q0.R = /Q0
Q1.R = Q1 * /Q0
+ /Q1 * Q0
Q2.R = Q2 * /Q1
+ Q2 * /Q0
+ /Q2 * Q1 * Q0
Q3.R = Q3 * /Q2
+ Q3 * /Q1
+ Q3 * /Q0
+ /Q3 * Q2 * Q1 * Q0
Q4.R = Q4 * /Q3
+ Q4 * /Q2
+ Q4 * /Q1
+ Q4 * /Q0
+ /Q4 * Q3 * Q2 * Q1 * Q0
Mini8085-3.072MHz.pld: Q2-Q0 implement divide by 5 frequency divider, Q3 and Q4 stages divide the frequency further by 2 and 4 respectively.
Q0.R = /Q2 * /Q0
Q1.R = /Q2 * /Q1 * Q0
+ /Q2 * Q1 * /Q0
Q2.R = /Q2 * Q1 * Q0
Q3.R = Q3 * /Q2
+ /Q3 * Q2
Q4.R = Q4 * /Q3
+ Q4 * /Q2
+ /Q4 * Q3 * Q2
These equations activate /ROMCS and /RAMCS signals:
The /ROMCS is active (LOW) when 8085 IO/M signal is LOW, indicating a memory access, and either A15 is LOW (lower 32 KiB of memory address space) and SWAPMEM is inactive (HIGH), or then A15 is HIGH (upper 32 KiB of memory address space), and SWAPMEM is active (LOW).
The /RAMCS is active (LOW) when 8085 IO/M is LOW, indicating a memory access, and either A15 is HIGH (upper 32 KiB of memory address space) and SWAPMEM is inactive (HIGH), or then A15 is LOW (lower 32 KiB of memory address space), and SWAPMEM is active (LOW).
/ROMCS = /IOM * SWAPMEM * /A15
+ /IOM * /SWAPMEM * A15
/RAMCS = /IOM * SWAPMEM * A15
+ /IOM * /SWAPMEM * /A15
This equation activates the /USARTCS signal. It is active (LOW) when 8085 IO/M signal is HIGH, indicating an I/O port access, address lines A7-A4 are LOW, and address line A3 is high. So that USART is selected using 00001xxxb addresses (8h-0Fh).
/USARTCS = IOM * /A7 * /A6 * /A5 * /A4 * A3
Link to the project on Mouser.com - View and order all components except of the 8085A CPU, the 8251A USART, and the PCB.
Link to the project on OSHPark.com - View and order the MiniMax8085 PCB.
MiniMax8085 uses MON85 Software Debug Monitor For the 8085/8080 written by Dave Dunfield. Specifically it was tested with the improved by Roman Borik version 1.2: mon85-v12-mini85.zip. This version adds support for undocumented 8085 instructions and flags.
The famous Tiny BASIC 2.0 written by Li-Chen Wang and modified by Roger Rauskolb, runs on MiniMax8085 with very little modifications: The 8251 USART I/O address needs to be updated, and its initialization parameters need to be slightly updated - to use 1 stop bit instead of two, and to enable CTS/RTS flow control. Also the RAM addresses need to be updated to start from 8000h.
For your enjoyment the original Tiny BASIC article from the December 1976 issue of Interface Age magazine - TinyBASIC-2.0.pdf, the source files and the ROM image - tinybasic-2.0-mini85.zip, are provided.