Table of Contents
The SBC V2 is a Zilog Z80 processor board. It's a 100x160mm board that is capable of functioning both as a standalone SBC or as attached to the ECB bus.
- 4Mhz Zilog Z80 CPU
- Up to 512Kb paged SRAM (: Add link to the paging description)
- Up to 1Mb EPROM or FLASH ROM.
- Serial Interface (16550 Uart)
- Parallel interface (8255), can be extended to support IDE interface via small board
- Real Time Clock (DS1302)
- Battery backup for RTC and SRAM.
- Standard ECB bus interface
- Standard PC drive connector power supply interface using +5V only
- Reset button with external connector
- Status LED
The latest SBC V2 schematic is available here: :boards:sbc:sbc_v2:sbc-v2-003-sch.pdf
Also, here's the board's PCB layout: :boards:sbc:sbc_v2:sbc-v2-003-brd.pdf
Kicad files for board manufacture: :boards:sbc:sbc_v2:ecb_sbc_v2-003-kicad.zip
A description of the circuit operation can been seen here: http://obsolescence.wixsite.com/obsolescence/the-n8vem-sbc
There is an error in the board layouts of sbc-v2-003 compared to the original schematic that results in the external reset not working in Kontron mode.
To configure the board to work in Kontron mode with the external reset coming from the backplane the following workaround can be made.
- Pin 3 on K13 needs to be jumpered to Pin 2 of P6 (Reset switch jumper) - this connects the backplane reset input pin (c31) to the reset circuit input.
- Pin 1-2 needs to be jumpered on K13 - this connects the /reset circuit output to the backplane reset out pin(c26).
The following table outlines the correct jumper settings for the SBC V2 board:
|Board Reference||Jumper Description|| |
Installed - allows you to use the common battery backup on the ECB bus (pin A24).
Not installed - means either a local battery is used or no battery backup at all.
|JP2||One bit input port||X||
Installed - enables the one bit input port. This is currently
unused although could be used for external input if desired like a button or other things.
Not installed - disables the one bit input port.
|K1||U2 EPROM chip pins (32-pin or 28-pin)||X *||32-pin EPROM used in U2 (ex. 27C080 1MBx8 EPROM) - default|
|X||28-pin EPROM used in U2 (ex. 27C256 EPROM)|
|K2||UART side hardware handshaking (DSR, CTS)||X *||DSR (this should be paired with K3 - DTR) - default|
|X||CTS (this should be paired with K3 - RTS)|
|K3||UART side hardware handshaking (DTR, RTS)||X *||DTR (this should be paired with K2 - DSR) - default|
|X||RTS (this should be paired with K2 - CTS)|
|K4||Serial side hardware handshaking (DSR, CTS)||X *||DSR (this should be paired with K5 - DTR) - default|
|X||CTS (this should be paired with K5 - RTS)|
|K5||Serial side hardware handshaking (DTR, RTS)||X *||DTR (this should be paired with K4 - DSR) - default|
|X||RTS (this should be paired with K4 - CTS)|
|K6||U2 chip type (27C080 EPROM, 29C040 flash)||X *||27C080 EPROM used in U2 - default|
|X||29C040 flash used in U2|
|K7||U23 SRAM (512K or 128K)||X *||512K chip used in U23 - default|
|X||128K chip used in U23|
|K8||U2 chip type (27C080 EPROM, 29C040 flash)||X *||27C080 EPROM used in U2 - default|
|X||29C040 flash used in U2|
|K9||Parallel Port power control (pin 25)||X *||GROUND - default|
|X||VCC ( WARNING - this setting will send VCC power down pin 25 of the parallel port which may potentially damage connected device)|
|K10||MCPL (Memory Page Config Latched)||X *||32K upper RAM fixed/32K lower RAM switchable memory map - default|
|X||48K upper RAM fixed/16K lower RAM switchable memory map (banked)|
|K11||MCPL (Memory Page Config Latched)||X *||32K upper RAM fixed/32K lower RAM switchable memory map - default|
|X||48K upper RAM fixed/16K lower RAM switchable memory map (banked)|
|K12||Bus Interrupt (pin A23)||X *||Internal UART interrupt - default|
|X||External ECB interrupt|
|K13||ECB/Kontron Reset configuration||X *||ECB legacy: pin C-31 is Reset OUT to peripherals - default|
Kontron compatible: pin C-31 is Reset IN from a SPST pushbutton pin C-26 is Reset OUT to peripherals.
N.B.: All boards in a system must use the same setting. Older boards don't have this jumper; hence, 1-2 is specified as the “default” setting. Newer systems should use the Kontron setting, since the newer backplanes have the Reset IN connector for pin C-31. (JRC 2015-7-6)
* = default setting
Serial Cable Instructions
The SBC V2 doesn't have any video capabilities in its solitary form. Therefore, in order to test it, you will need to connect it to a serial terminal (which will provide the keyboard input and monitor output). The easiest way to do this is to construct a cable which will provide a serial port (with a D-sub connector or DE-9 plug) which will plug into a “host” computer running a serial terminal emulation program. This program will allow you to interface with the SBC V2 board using the host computer’s keyboard and monitor.
First, you must build a cable with an IDC-10 plug on one end (plastic rectangular connector with 2 rows of 5 pins) and a female DE-9 plug (ie. a serial port plug) on the other end.
The female DE-9 plug is what you will plug into the serial port of your host computer. Serial ports (on the back of the computer) are male ports (ie. they have pins), so the plug at the end of this cable must be a female plug (they have holes). It's not recommended to use accessory serial cables to make this connection (such as null modem cables, etc.). This is because many such cables are wired for specific applications, and may not work with your SBC V2 board. For instance, a serial data transfer cable is wired very differently from a “straight-through” serial cable (pin 1 to 1, 2 to 2, etc.) which is different from a null modem cable. Because of this cable inconsistency, it's preferred to build the complete custom cable from the beginning knowing exactly what pin is connected where and why, and not to use any serial extension cables. The exception to this is using a serial cable that you know is wired as a “straight through” cable (with each pin on one plug connected to each pin on the other plug: 1 to 1, 2 to 2, etc).
The following cable layout shows what is being connected where in this cable:
|IDC-10 side||DE-9 side|
Pin 1 on the IDC plug is marked with an embossed triangle on the plug, and this pin corresponds to pin 1 on the pcb which is marked with a square solder hole (at the lower-right most position of the plug on the SBC V2 pcb). The pins on the DE-9 plug are usually marked right on the plug itself in tiny numbers. Strip some wires and solder away. Instead of stripping wires and soldering manually, you can also use ribbon cable and special “direct connect” plugs that connect directly to the ribbon cable without soldering (they have rows of metal “pins” that press down and penetrate the ribbon cable to make the connections). Because of the non-standard pin connections that are needed in this cable (per the above table), however, you will likely need to do some soldering or “custom connecting”.
Always double and triple check where you’re soldering something before you solder it. When you’ve built your cable, use your multimeter to check connectivity between each pin on the IDC-10 side and the DE-9 side according to the arrangement above to make sure you got it right.
In order to test connections in a plug you cannot stick the multimeter lead into the hole (because it will not fit). Instead, take a spare piece of wire, stick it into the hole for the pin you want to test, and then touch the multimeter lead to that wire.
Flow control considerations:
ROMWBW will automatically identify the type of serial chip installed. Depending on the capability of the serial chip, flow control may or may not be available. Chip data sheets cannot be relied upon to accurately identify the chips capability.
In the absence of flow control, guidelines for baud rate settings are:
4Mhz CPU Crystal - 38400 baud
8Mhz CPU Crystal - 57600 baud
Baud rate can be changed using the CP/M MODE program i.e. MODE COM0:57600,8,N,1 /P
If garbled characters are seen on the display or serial file transfers fail, a lower baud rate should be tried.
Full list of parts::boards:sbc:sbc_v2:sbc-v2-parts-list.pdf
See here for minimum build and parts substitution guidelines.
There is extensive firmware support for the SBC V2 and associated ECB peripheral cards. Currently there are two firmware builds still being actively developed - UNA and ROMWBW.
See here for current software builds and information on historical projects.
A debug boot ROM can be installed for testing - try James Moxham's ROMIMAGE.BIN from here.
REAL TIME CLOCK (RTC)
The DS1302 real time clock can be set under CP/M using the rtc utility program.
Loading CPM... CP/M-80 Version 2.2C for the N8VEM, October 2008 Run XM from A drive, this downloads file to B drive A>rtc Start RTC Program RTC: Version 1.0 RTC: Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut H)elp RTC: trickle charger disabled. RTC>
Set the time and date with the Init command first and then use the Set command to program it.
RTC.COM can also be used to set up trickle charging for the backup battery or super capacitor if connected. More Information on charging Super Capacitors can be found here: https://www.maximintegrated.com/en/design/tools/calculators/product-design/supercap.cfm
The utility can also set and read the RTC memory.
A single color or bicolor LED can be installed for the status LED. The LED monitors the status of the HALT line from the Z80 CPU. Consider the color selection and orientation when choosing. A red/green LED is ideal and logically should show green when cpu is running and red when halted. Or in the case of a single colour LED, on when cpu is running and off when halted. It is wise to not fully solder in the LED until the orientation has been checked to confirm the right sequence. Or, you could install a pin header and run flying leads to an LED mounted in a case,
The HALT status can be initiated by booting CP/M and running the DDTZ debugger, loading and executing a HALT instruction.
B>ddtz DDTZ v2.7M by CB Falconer. CPU=Z80 -a100 0100 hlt 0101 -g100
The SBC can be configured with 128Kb or 512Kb RAM and up to 512Kb ROM. The Z80 processor can only access 64Kb at one time, so the additionally memory is accessed through a memory paging scheme.
The memory paging system can be configured in two different ways but the default is to be set with 32Kb of RAM fixed at the top 8000h-FFFFh memory range and for the bottom 32Kb 0000h-7FFFh being selectable from either the RAM or ROM chips. This 32Kb/32Kb configuration is what is supported by the ROMWBW software package.
Under the 32Kb/32Kb configuration, the top 32Kb is mapped to the last 32Kb of the 128Kb or 512Kb RAM chip and the lower 32Kb is selected from RAM or ROM by writing the required address line configuration to the RAM or ROM memory page configuration latch.
One Bit Input Port
Bit 6 of RTC port $70 is connect to an on board jumper JP2 which can be read by software. By default it is tied high. Removing jumper JP2 will result in the being tied low (=0).
Effectively this creates a configurable jumper setting which the ROMWBW bootrom can use for determining the primary communications console.
This facility is not enabled by default in ROMWBW and the setting is ignored. To enable, rebuild the ROMWBW package with the CRTACT setting set to true. The CRT type can also be configured at this time:
CRTACT .SET TRUE ; CRT ACTIVATION AT STARTUP VDAEMU .SET EMUTYP_ANSI ; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
This will cause ROMWBW to check the status of BIT 6 at startup. If “0” (jumper removed) it will change the primary communications console from the Serial UART to the first CRT console found. If a CRT console is not found it will default back to the Serial UART. If BIT 6 = “1” (jumper in place) it will boot as normal with the primary console using the Serial UART.
Boot "BEEP" modification
There is no inbuilt sound on the SBC V2 board. Complex sound output can be achieved with the ECB-SCG (Sprite-Colour-Graphics) board.
Rudimentary sound support can be add the SBC V2 by utilizing one of the unused outputs of the RTC interfacing latch and connecting a simple amplifier to this output.
On U18 74LS174 connect a ground wire from pin 8 and a signal wire from pin 2 to an amplifier. Generic LM386 amplifiers are available from many sources and work well.
With this addition and the
SPKENABLE setting set to
TRUE in ROMWBW, the SBC V2 will issue a beep sound on bootup.
The SBC V2 uses address 60h - 7Fh for on board peripherals. Address decoding is not complete so some address ports are duplicated within this address range. All other I/O address ranges are exported to the ECB.
|82C55 PPI||Parallel Port||60h-63h ( & 64h-67h)|
|16550 UART||Serial Port||68h-6Fh|
|DS1302 RTC||Real Time Clock||70h ( & 71h-77h)|
|RAM||RAM bank select latch (Write Only)||78h ( & 79h)|
|ROM||ROM bank select latch (Write Only)||7Ch ( & 7Eh)|
Changes from V1
Information regarding V1 can be found here.