74HC - Apollo Guidance Computer

This project would be impossible without massive amounts of work done by people who are much more well versed in the AGC then myself. I first though of this as a “pie in the sky” retro computing project in 2013 - but my ability to actually attempt to build it now is largely because of this prior work. Any accolades are much more applicable to them, then they are to me.

• The entire team at MIT and throughout the country who created the original AGC hardware & software
• Mike Stewart for more things then I can probably list, but these are some big ones:
  • agc_hardware repository which has the KiCAD schematics
  • agc_simulation repository which has the corresponding Verilog
  • agc_monitor repository which has the FPGA implementation of the AGC EGSE rack
  • Custom fork of NASSP for interfacing with the agc_monitor
  • Pin Inspector website which allows the signals on the AGC backplane to be visualized
• Ronald Burkey and other contributors to the Virtual AGC project, which has collected scans of 1000s of pages of Apollo documentation from the National Archives and made them available in an extremely comprehensive website/database
• The AGC Restoration Team who restored AGC SN 014 to operation - Marc Verdiell, Mike Stewart, Ken Shirriff, and Carl Claunch
  • The awesome 29-part YouTube series on this restoration was a huge motivator for me
  • The entire team was very gracious to answer many questions that I had at VCF West 2019

This is a project to create a working physical implementation of the Apollo Guidance Computer (AGC), using mostly 74HC series logic chips, which can be interfaced with the Orbiter Space Flight Simulator and a custom fork of the NASSP add-on to fly simulated missions using the physical 74HC-AGC.

I also hope to learn some new skills for my retro project toolbox during this project, such as:

• Layout of 4+ layer PCBs
• Hand soldering and reflow oven soldering of surface mount ICs
• Verilog simulations and FPGA synthesis

Any complex engineering project needs requirements, and the 74HC-AGC is going to be a complex multi-year effort. These are the requirements that I am holding for the 74HC-AGC:

• Assembled unit + enclosure shall have approximately the same volume envelope as the original AGC
• Assembled unit shall have a similar physical layout to 'Tray A' of the original AGC. Module to module spacing may be updated to allow all modules to fit in the available footprint.
• External interface connectors shall have the same pinouts as the original AGC
• Completed unit shall be capable of interfacing with Mike Stewart's forked version of NASSP to simulate Apollo missions
• Completed unit shall be capable of interfacing with a future DSKY unit
• Completed unit shall interface to the outside world via 3.3V CMOS level logic
• Design of the input/output modules shall allow for future upgrade with modules that support interfacing with restored real Apollo hardware, should such hardware become available

Things that are not requirements:

• This is not an exact physical replica to match the original mechanical drawings of the AGC. For example, the replacement of Tray B with a greatly simplified module using modern EERPOMand MRAM chips allows for 'Tray A' to essentially double in height, so 74HC-AGC modules will be about 2x as tall as real AGC modules.

Q: Will this move from a 'builder page' to being a traditional 'Retrobrew Computers' project with the PCB files available?

A: My hobby time is frequently limited due to work and family obligations and this build is a massive endeavor (the back plane PCB will be 12“x24” and 8-12 layers). At this time I'd like to focus my time on getting the build working which may take 2+ years to get through all of the modules. At that point I may evaluate making PCB files available for others. If I ever decide to stop working on the project, I will also make whatever I have done available for others to use as a starting point. (This is just my current thinking on this topic, and will continue to evaluate going forward)

Building the A1 Scaler module was intended to be proof of concept prior to using the same chip layout for all remaining boards. One change I will make on future boards is to go to 0805 capacitors for the 0.1uf decoupling caps, to make it at little easier to populate the boards - 0603s were very difficult to handle manually. Another change is to do an inspection with my USB microscope before proceeding straight to testing - I got a bit excited and just did a quick visual, and there were ~6 pins I missed while soldering that messed up the signals for CHAT13 and onward. A quick rework and everything worked perfectly. Never skip QA!

Proper operation of all output signals was verified through a combination of oscilloscope, logic analyzer, and using a Parallax Propeller 2 to read the status of bits CHAT13, CHAT14, and CHBT01-CHBT14 and log to a terminal window on a PC. CHBT14 has a period of 23.3 hours, so the Propeller was a great tool to track the status of the slower signals coming out of the chain of clock dividers.

The next item of interest was to check the Tpd values through the various flip-flop stages and modify the agc_simulation Verilog code to produce matching results and confirm that the simulation still runs with delays matching reality.

Looking at signals F04A and F18A with the logic analyzer allowed me to measure the delays of the rising and falling edges of the pulses:

The agc_simulation repository defaults to a 9ns delay for each gate, I updated and re-ran that value for cases of 8ns and 7ns as well to build up a dataset to compare to reality.

F04A Rising → F18A Rising

• Physical 74HC @ 3.3V = 194ns
• agc_simulation with 7ns delays = 196ns
• agc_simulation with 8ns delays = 224ns
• agc_simulation with 9ns delays for each gate (default value in the simulation) = 252ns

F04A Falling → F18A Falling

• agc_simulation with 7ns delays = 396ns
• agc_simulation with 8ns delays = 448ns
• Physical 74HC @ 3.3V = 475ns
• agc_simulation with 9ns delays for each gate (default value in the simulation) = 503ns

The physical hardware seems to be approximately equivalent to a delay of 7ns if the rising edges are considered, and 8.5ns if the falling edges are considered.

There do not appear to be any immediate issues with the simulations run as fast as 7ns to better match with reality, but I am still learning the ins and outs of the simulation process.

Some notes on running the simulations: I updated the Makefile so I could use the .v files present on github, vs re-generating them from the KiCAD files (which requires a custom fork of KiCAD 4) I also updated the agc_test.v code to output the waveform data in the .fst format instead of the .lxt2 file format, since .fst is generally a newer/faster/smaller format. I also had to extend the duration of the simulation out to 4 seconds in order to catch a pulse on F18A.

This will be the first update on this Wiki. I started actually doing KiCAD work in July, with a lot of interruptions. Thus far I've completed the following:

• Moved all the agc_hardware schematics into KiCAD 6 with the new file formats
• Outputted part BOMs of all the modules from the schematics to assess part costs
• 'Right Sized' the connectors on each of the modules in the original agc_hardware to use the smallest # of DIN 41612 connectors possible
  • Created schematic symbols for various combinations of DIN 41612 connectors
• Created a backplane PCB schematic using the modules in agc_hardware
• Created a backplane PCB layout from the schematic, including choosing length of modules
  • Created PCB footprints for the various combinations of female DIN 41612 connectors
• Routed a proof-of-concept backplane PCB using Freerouting to make sure this will work in the future - success!
• Stacked up mechanical part sizes in the Z direction to determine height of modules
• Created PCB routing for A1 Scaler module as a proof-of-concept module
  • Created PCB footprint for different combination of male DIN 41612 connectors
• Fabricated, assembled, and tested the A1 Scaler Module

The proof-of-concept backplane layout (several connectors are still missing from this proof of concept - the main goal of this was to ensure the Freerouting could handle a board of this complexity):

The A1 Scaler module during layout, assembly and testing: