CPLD Educational Board with 6502/Z80 Processor, CPLD6502 Rev 1

Introduction

CPLD Trainer explores the world of complex programmable logic device (CPLD) and how it interact with 6502, Z80, and other processor and memories. Discussion about the CPLD trainer can be found here. This is the link to previous version (rev0) of CPLD trainer.

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Features

Design Files

Z80 Implementation

Z80 implementation requires 14.7MHz oscillator, CMOS Z80, 512K RAM (e.g. AS6C4008), and 512K flash (e.g. SST39SF040)

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Z80 CPLD design file to run ROMWBW ← updated release 6/5/22 with added I2C function

ROMWBW program for 512K boot flash such as SST39SF040

Game of Life, Gosper gun. Require 128×64 OLED display installed on I2C connector (see picture below). Load .hex program with ROMWBW monitor and run from 0x1000.

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6502 Implementation

6502 implementation requires 7.37MHz oscillator, W65C02, 512K RAM (e.g. AS6C4008), and 512K flash (e.g. SST39SF040)

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6502 CPLD design file

6502 monitor


Training Sessions

Discussion about the CPLD6502 trainer can be found here. The sessions were done with rev0 of CPLD trainer; because of small differences between rev0 and rev1 design, some CPLD design files are updated to work with rev1 design.

Design files and software for the various sessions

Jan 27, 2022 ,Session 1, Initial power up and first CPLD program. Session 1 CPLD design files

Jan 28, 2022, Session 2, multiplexing 7-segment displays. Session 2 CPLD design files

Jan 30, 2022, Session 3, 6-digit 7-segment display. Session 3 CPLD design files

Jan 31, 2022, Session 4, lookup table and true 6-digit hex display. Session 4 CPLD design files

Feb 1, 2022, Session 5, 6502 NOP test. Session 5 CPLD design files

Feb 2, 2022, Session 6, tester for 6502. Session 6 CPLD design files

Feb 3, 2022, Session 7, EPROM and RAM decode. Session 7 CPLD design files

Feb 4, 2022, Session 8, RAM diagnostic. RAM diagnostic source files

Feb 5, 2022, Session 9, 6502 SBC with serial port in CPLD. Session 9 CPLD design files

Feb 6, 2022, Session 10, Monitor for 6502 SBC. Session 10 CPLD design files, CPLD6502 SBC monitor software.

Projects for 6502-based Trainer

VGA beam racing is a W65C02 overclocked to 25.175MHz, the 60Hz 640×480 VGA dot clock, such that 6502 fetch a byte every 8 clocks that's shifted out to VGA monitor at pixel clock rate. This results in monochrome 640×480 resolution images.

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builderpages/plasmo/6502/cpld6502/cpld6502r1.txt · Last modified: 2023/04/22 23:51 by plasmo
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