Zero-Glue-Logic 6502 Prototype, Prog65ZG

This is a zero-glue-logic 6502 single board computer prototyped on a Prog65 rev0 pc board.

This is the link to rev0 of ZG6502, the pc board version of zero-glue-logic 6502 SBC.

• W65C02-based single board computer prototype
• No glue logic
• 32KB RAM located at 0x0-0x7FFF
• 16K EPROM located at 0xC000-0xFFFF briefly after reset
• W65C51 ACIA
• 7.37MHz system clock

Prog65ZG is a traditional 6502 computer with RAM, EPROM, and serial I/O. The one unusual feature is the cascaded reset logic consists of two MCP130 reset supervisors. At power cycle the primary reset supervisors is in reset for the nominal 350mS and holds the secondary reset supervisor in reset. When the primary reset supervisor releases the reset, the secondary reset supervisor remains in reset for another 350mS. The primary reset output is connected to 6502's reset while the secondary reset output is connected to chip select and output enable of EPROM. The cascaded reset logic enable EPROM to be accessed at location 0xC000-0xFFFF for 350mS after 6502's reset is released. During this time, 6502 copies the contents of EPROM to RAM and then jumps to RAM and loop long enough for the secondary reset supervisor to finish its reset. Afterward the memory map consists of RAM at 0x0-0x7FFF, serial port (W65C51) at 0x8000-0xBFFF, and no device from 0xC000-0xFFFF. Future I/O or memory devices may use the empty 16K space from 0xC000-0xFFFF.

Schematic

Engineering change to Prog65 rev0

Simple monitor for Prog65ZG. This is a simple 4-function monitor that loads Intel Hex file, displays and modifies memories, and runs program at specified location.