CB030 Development Blog
CB030 will have a 25MHz 68030 (because I have lots of them), 16 Meg DRAM initially but 64/128 Meg final, 512K boot flash, compact flash mass storage, dual serial ports, and an I/O expansion port on a 4“ x 4” pc board.
The design will have mostly through-hole components, but to reduce complexity and cost of components and PC board, it will have a surface mounted CPLD as glue logic. CB030 will be designed to be constructed in stages.
- Stage 1, SMT CPLD is assembled and programmed to perform basic diagnostic
Stage 2, 68030 and DRAM are added; CPLD has a “serial bootstrap” feature where program can be loaded through the CPLD-based serial port to test the memory and CPU functionalities Stage 3, boot flash is added; the bootstrap program is loaded through the serial bootstrap feature to program the boot flash. Afterward the normal bootstrap mode is enabled to boot off the flash memory. The ability to switch between serial bootstrap and flash bootstrap will be retained so future updates of bootstrap flash will always have the serial bootstrap as backup in case of update failure. This also save the end users from having to have a EPROM programmer.<– Note, the staged assembly is deleted because CPLD does not have sufficient I/O pins.
- Stage 4, Serial ports and compact flash interface are added. CP/M68K is the initial OS, but hopefully a more powerful OS can be developed later on.
The staged assembly features allow CB030 to be build by most hobbyists except stage 1. A shop or an individual (such as myself) can assemble the CPLD, program and test it, then sell the board with programmed CPLD at a nominal fee, say $15 or so. The buyers can procure the remaining components and complete the assembly, stage by stage. Of course a complete kit can be provided or even a fully assembled/tested board, but many (most?) people probably like to assemble their own.
1/4/20 Preliminary schematic generated. Need to do exploratory layout to assign CPLD pins optimally.
1/6/20 Exploratory layout in 2-layer is encouraging. Able to fit the design in 4“x4”
Received the pc board. Populate the CPLD so it can be programmed and serves as a tester
Populate the core components. I'm now able to communicate with CB030 via serial port!
Porting EhBasic to CB030 and run the ASCII benchmark in 24 seconds. I still need to turn on the data cache and enable the cache burst fill. I also need to reduce the wait states for accessing the DRAM so the benchmark number should improve significantly.
CP/M68K is running on CB030! The EPROM has enough space to put a few critical CP/M files so I can format the DOM disk and transfer files from PC to DOM disk. This way I can KERMIT the entire CP/M68K distribution files into the DOM disk. I compiled the ASCII Mandelbrot program with the BASIC compiler and execute it.
Up to now the DRAM has a wait state of 2. I'm looking at the timing closely and decided that with 60nS DRAM and 24MHz 68030, I can run it 0 wait state, just barely. So that's what I did. Now the EhBasic benchmark takes 18 seconds and the same benchmark running in CP/M68K takes 51 seconds. The difference is due to the efficiency of the EhBasic and that fact instruction cache is turned when EhBasic is running. Now I can really tell the difference in speed!
Built up 2nd CB030 to make sure I wasn't just lucky with the first built. Yep, the 2nd one works just like the first one.
I have successfully built 4 working rev0 CB030. One has been shipped to Cecil B. since the design is named after him.
The picture below shows a CB030 with Quad Serial card (foreground) plugged in the I/O expansion port. The vertical SIMM card is 64meg memory. The Quad Serial card was originally designed for RC2014 bus, but with small modification it also works with CB030 I/O expansion bus which is quite similar to RC2014 connector definition.