CB030_Rev1, A 68030 SBC for Hobbyists

Introduction

CB030 is named after Cecil B. a 680×0 enthusiast who has motivated me to update the Tiny030 design and made it available to hobbyists. It is based on a 24MHz 68030, 16 Meg DRAM initially but 64/128 Meg final, 512K boot flash, compact flash mass storage, dual serial ports, and an I/O expansion port on a 4“ x 4” pc board. The emphasis is on a capable yet economical foundation that hobbyists can build on. The design will have mostly through-hole components, but to reduce complexity and cost of components and PC board, it will have a surface mounted CPLD as glue logic. The surface mounted CPLD can be assembled and programmed by an individual such as myself or assembly shop and the remainder assembled by the end users.

Here is link to CB030 rev0

www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_cb030_cb030_rev1_cb030_rev1_annotated.jpg

Features

  • 24MHz 68030
  • 512K bootstrap EPROM
  • 72-pin SIMM, accept 4/8/16/32/64/128 meg
  • EPM7128S glue logic
  • 68681 DUART with 2 serial ports and discrete I/O
  • Console serial interface 38400, N-8-1
  • 44-pin IDE Compact Flash interface
  • CP/M68K ready
  • 8-bit I/O expansion bus
  • Economical 4“x4” 2-layer pc board
  • 5V 1Amp

Functions

CB030 is simple to build but with sophisticated capabilities. This is possible with an economical but capable Complex Programmable Logic Device (CPLD), Intel (formerly Altera) EPM7128S. All address decode, DRAM controller, dynamic bus sizing, cache interface, and RAM/EPROM remapping are done in the CPLD.

When CB030 is reset or powered on, its entire memory map, except the top 32K of the memory (0xFFFF8000-0xFFFFFFFF) is mapped to the EPROM. The DRAM which is normally located at 0x0 is not accessible. However, by accessing (read or write) a location at 0xFFFF8000, the EPROM is mapped to 0xFE000000-0xFEFFFFFF and DRAM is now visible starting from 0x0.

Design Information

Schematic

Gerber photoplot, Rev 1.1

Bill of Materials

EPM7128SQC100 design files The CPLD is updated to include an internal 100Hz interrupt source that can be turn on or off under software control. Revision number is now assigned to CPLD. The CPLD with internal 100Hz interrupt is version 1.2

Memory map

Discrete I/O port pictorial diagram

Software

CB030 monitor

CP/M68K BIOS

CP/M68K distribution files

CP/M68K CCP/BDOS

EPROM programming file for 512Kx8 EPROM

16 meg DRAM memory diagnostic

64meg DRAM memory diagnostic

Linux 4.9 port to CB030

Many thanks to Mike McDonald for porting Linux 4.9 to CB030. You can find details here.

Manuals and Instructions

Getting Started with CB030

Pictorial construction guide

Setting up a new CB030. This is continuation of the pictorial construction guide

How to update CPLD

CB030 development blog

CB030 Monitor Manual

Customerization

Upgrade to 16-bit CF interface from the original 8-bit interface.

Adding 100Hz interrupt capability in CPLD. Accessing addresses 0xFFFF9800-0xFFFF9FFF will turn on 100Hz interrupt source in CPLD. The interrupt acknowledge is level 2 autovector. Accessing address 0xFFFF9000-0xFFFF97FF will turn off the interrupt source. 100Hz interrupt is turned off at power up.

CPLD equations

(3/26/20)Updated CPLD with internal 100Hz interrupt. This fixes the large & slow combinatorial tree of divide-by-240000 resulting in intermittent operation at 24MHz.

Quick test program. Turning on the interrupt which outputs a dot ('.') on monitor for each 100Hz interrupt; it will turn off interrupt after few seconds and return to the monitor


To Do

  • explain memory map of 4/8/16/32/64/128 DRAM
  • diagram of the 7-seg display
  • how to load CP/M68K into a new CF disk
  • monitor command to enable hardware handshake
builderpages/plasmo/cb030/cb030_rev1.txt · Last modified: 2020/04/14 07:33 by plasmo
Driven by DokuWiki Recent changes RSS feed Valid CSS Valid XHTML 1.0