Engineering Changes for Rev0 PCB of EaZy80

Link to original schematic of rev0 EaZy80

Link to rev0 EaZy80 completed with engineering changes

• Controlling two banks of 64K RAM: cut ground trace on component side connecting to pin 2 of U3 (RAM); solder a 4.7K resistor from pin 2 of U3 to ground; connect pin 2 U3 to pin 11 U4 (KIO)
• Controlling RAM output enable: connect U3 pin 24 to U4 pin 30
• Second serial port handshake: connect P2 pin 1 to U4 (KIO) pin29.
• Console serial port handshake: connect P3 pin 1 to U4 pin 14
• Serial ports clock source: connect U3-56 to U3-73 to U3-16 to U3-4
• Enable console handshake: connect U3-8 (/DCDA) to ground, pull U3-9 (/CTSA) to ground through a 1K resistor.
• Enable 2nd serial port handshake: connect U3-7 (/DCDB) to ground, pull U3-6 (/CTSB) to ground through a 1K resistor.
• Enable DMA: pull U3-45 (ARDY) and U3-46 (/ASTB) to VCC through a 4.7K resistor.