OVRCLK65, Overclock Experiment Prototype for W65C02 and W65C816


While WDC's W65C02 and W65C816 are rated at 14MHz, it is well known that they can operate at much higher clock. This is especially true since the design have been ported to smaller 0.6u technology. OVRCLK65 is simple 65xx design centered around a CPLD to check out the upper speed limit of W65Cxx CPU. Discussions about OVRCLK65 can be found here.




The OVRCLK65 prototype board is based on the ProtoRC board. A 40-pin DIP socket is installed on the prototype area and wired to test points of ProtoRC. The following are the features of the OVRCLK65 prototype:

  • DIP40 socket to accommodate W65C02 or W65C816
  • EPM7128SQC100 CPLD
  • Full size can oscillator
  • Reset supervisor

Theory of Operation

The 128-macrocell CPLD, EPM7128S, provides 64 bytes of boot ROM, serial port, and glue logic to check out the target processor.

Design Files for W65C02


CPLD design files in Altera Quartus. CPLD design is in schematic form. This link is a PDF of the schematic.

builderpages/plasmo/ovrclk65.txt · Last modified: 2021/07/21 15:13 by plasmo
Driven by DokuWiki Recent changes RSS feed Valid CSS Valid XHTML 1.0