Table of Contents
Mod_29M, Overclock SC114 and Other Modifications
Introduction
SC114 is an economical easy-to-build Z80 SBC designed by Steve Cousin. It consists of a Z80, 128KB RAM, and 32K ROM. It communicated to the outside world via bit-bang serial port nominally at 9600bps with 7.37MHz CPU clock. The design is quite simple and lend itself to be overclocked up to 29.5MHz.
Motivations for SC114 Modification
The primary motivation is to run SC114 4 times faster to 29.4912MHz with the associated serial communication at 38400bps. The other goal is to increase the ROM size to 64KB to store more applications and to implement “shadow write” capability so RAM contents can be written while executing in ROM.
Prepare bare PCB
Schematic of Mod_29M
*Added A15 to W27C512 to have 64K ROM
* Shadow write capability such that when ROM writes to itself, it modifies the RAM at the corresponding address
*74ls259 addressable register is modified so Q2 to RAM output enable, Q3 to RAM chip select (active high), and Q7 to ROM chip select (active low)
Q2 RAM nOE | Q3 RAM CS high | Q7 ROM nCS | Description | |
---|---|---|---|---|
Reset (ROM only) | 0 | 0 | 0 | ROM enabled, RAM disabled |
Shadow Write | 1 | 1 | 0 | ROM enabled, RAM shadow write |
Contention | 0 | 1 | 0 | ROM enabled, RAM enabled |
RAM only | 0 | 1 | 1 | ROM disabled, RAM enabled |
Software
Original SC Monitor (SCM-S2-2022-02-27-Monitor-v130-BIOS-v130-SC114) is patched at two places.
- Modified the hardware handshake to give RTS assertion more time. Insert this starting at location 0x2005
00002005 AF A 2 xor a 00002006 D3 20 A 3 out (20h),a 00002008 DB 28 A 4 xx in a,(28h) 0000200A E6 80 A 5 and 80h 0000200C 28 09 A 6 jr z,2017h 0000200E 10 F8 A 7 djnz xx 00002010 3E 01 A 8 ld a,1 00002012 D3 20 A 9 out (20h),a 00002014 C1 A 10 pop bc 00002015 AF A 11 xor a 00002016 C9 A 12 ret 00002017 3C A 13 inc a 00002018 D3 14 A 14 out (20),a
- Add initialization code to copy 64K ROM to 64K RAM before SCMonitor's own reset initialization code. Reset jumps to this code at 0x7F00 first:
A 1 ;12/7/22 A 2 ;prepare the hardware for SCMonitor A 3 ;copy ROM to RAM A 4 ;disable ROM A 5 ;I/O addresses: A 6 ; 0x38 ROM chip select, 0=ROM selected A 7 ; 0x8 LED, 0= LED on A 8 ; 0x10 RAM output enable, 0=RAM read enabled A 9 ; 0x18 RAM chip select, 1= RAM selected A 10 ;everything low at reset A 11 org 7f00h 00007F00 3E 01 A 12 ld a,1 00007F02 D3 10 A 13 out (10h),a ;disable RAM output 00007F04 D3 18 A 14 out (18h),a ;select RAM for shadow write A 15 ;shadow write to self for entire 64K 00007F06 21 00 00 A 16 ld hl,0 00007F09 11 00 00 A 17 ld de,0 00007F0C 01 00 00 A 18 ld bc,0 00007F0F ED B0 A 19 ldir 00007F11 AF A 20 xor a 00007F12 D3 10 A 21 out (10h),a ;enable RAM read 00007F14 3C A 22 inc a 00007F15 D3 38 A 23 out (38h),a ;disable ROM 00007F17 C3 CB 1C A 24 jp 1ccbh ;reset vector of SCMonitor
Results
It works reasonably well. R2 resistor at 10K is problematic because it is too weak to drive data line (D7) at high serial speed. Change it to 4.7K works better, but still flaky. There is a balance between CP2102 drive and Z80 drive. A tri-state data buffer should work better.
Hardware handshake now work.
Design works much better at 14.7MHz than 29.5MHz.
To Do:
Description of KIORC and CF disk plugged in SC114 with mod_29M
Software associated with KIORC for SC114 with mod_29M