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builderpages:plasmo:t68krc [2018/07/14 00:13]
plasmo
builderpages:plasmo:t68krc [2018/07/14 20:56] (current)
plasmo
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   * Target for CP/M-68K ver 1.3   * Target for CP/M-68K ver 1.3
   * 100mm x 76mm 2-layer pc board   * 100mm x 76mm 2-layer pc board
-  * 
  
 ===== Descriptions ===== ===== Descriptions =====
  
-Low cost without sacrificing performance is the design goal of Tiny68K. Cost control is achieved by:+Low cost without sacrificing performance is the design goal of T68KRC. Cost control is achieved by:
  
   * Two-layer PC board in 100mm x 76mm format. Many board manufacturers only charge 50 cents per board in quantity of 10 in this format,   * Two-layer PC board in 100mm x 76mm format. Many board manufacturers only charge 50 cents per board in quantity of 10 in this format,
-  * Memory in the form of single-chip 1Mx16 DRAM. Such modules can be purchased for $2-3 each on eBay+  * Memory in the form of single-chip 1Mx16 DRAM, 
-  * Low cost 5-Volt CPLD, Altera EPM7128, that is about $2-3 each from China,+  * Low cost 5-Volt CPLD, Altera EPM7128, that is about $3-4 each from China,
   * Use low-cost serial flash memory as the boot memory,   * Use low-cost serial flash memory as the boot memory,
   * Interface via pc board edge connector to a low-cost 44-pin IDE-CF module,   * Interface via pc board edge connector to a low-cost 44-pin IDE-CF module,
-  * No on-board RS232 transceiver because most USB-based serial port modules operate at the TTL level.+  * No on-board RS232 transceiver because most USB-based serial port modules operate at the TTL level
 +  * Low cost RC2014 expansion bus connector.
  
-Good performance is maintained by: *+Good performance is maintained by:
  
-16-bit wide data bus, +  * 16-bit wide data bus, 
- +  * 2-megabyte ​60ns DRAM operating at zero wait state (at 8MHz system clock),
-  * 16-megabyte ​SIMM72 ​DRAM operating at zero wait state (at 8MHz system clock),+
   * Fast serial flash loads monitor in 0.6 second after a reset or power on,   * Fast serial flash loads monitor in 0.6 second after a reset or power on,
-  * 16-bit wide bus-connected IDE interface operating with zero wait state at 8MHz,+  * 16-bit wide bus-connected IDE interface operating with two wait state at 8MHz, **<​-verify this**
   * Hidden CAS-before-RAS refresh cycle with no software overhead.   * Hidden CAS-before-RAS refresh cycle with no software overhead.
  
-Memory map +==== Memory map ====
- +
-RAM is from 0x0 to 0x1FFFFF,+
  
 +  * RAM is from 0x0 to 0x1FFFFF,
   * Serial Flash is from 0xFFD000-0xFFDFFF   * Serial Flash is from 0xFFD000-0xFFDFFF
   * IDE-CF is from 0xFFE000-0xFFEFFF   * IDE-CF is from 0xFFE000-0xFFEFFF
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   * RC2014 expansion bus is from 0xFF9000-0xFF8FFF. 2 wait states access <- **verify this**   * RC2014 expansion bus is from 0xFF9000-0xFF8FFF. 2 wait states access <- **verify this**
  
-===== Design Files =====+===== Design Files <- Need extensive updates ​=====
  
-Rev 1 {{:​boards:​sbc:​tiny68k:​tiny000scm_rev1.pdf|schematic}}+Rev 1 schematic
  
-Rev 1 {{:​boards:​sbc:​tiny68k:​tiny68k1.zip|Gerber files}}+Rev 1 Gerber files
  
-[[:​boards:​sbc:​tiny68k:​rev1partlist|Part list]]+Part list
  
-Tiny68K ​{{:​boards:​sbc:​tiny68k:​t68kbug.zip|Monitor debugger}}. The software is developed in the EASy68K tool chain. ​{{:​boards:​sbc:​tiny68k:​t68kbug_bin.zip|Programming binary}}  ​for serial EEPROM programmer (CH341).+Tiny68K Monitor debugger. The software is developed in the EASy68K tool chain. Programming binary for serial EEPROM programmer (CH341).
  
 Altera EPM7128 design files Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. Schematic in PDF format. Programming binary in .pof format. Altera EPM7128 design files Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. Schematic in PDF format. Programming binary in .pof format.
  
-  * 11/23/17 update: The original design files posted were incorrect. This is the correct version of the design files. Altera EPM7128 ​{{:​boards:​sbc:​tiny68k:​released_version_nov2017.zip|design files}}  ​Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. ​{{:​boards:​sbc:​tiny68k:​tiny68k_epm7128_release.pdf|Schematic in PDF}}  ​format. {{:​boards:​sbc:​tiny68k:​released_epm7128_program_binary.zip|Programming binary}} ​ in .pof format.+  * 11/23/17 update: The original design files posted were incorrect. This is the correct version of the design files. Altera EPM7128 design files Designs are created in Quartus 8.1, should be compatible with later version of Quartus. Designs are entirely in schematics. Schematic in PDF format. {{:​boards:​sbc:​tiny68k:​released_epm7128_program_binary.zip|Programming binary}} ​ in .pof format. ​** <- need revision**
  
-CP/M-68K {{:​boards:​sbc:​tiny68k:​tinybios_r4.zip|BIOSfor Tiny68K ​* }}+CP/M-68K {{:​boards:​sbc:​tiny68k:​tinybios_r4.zip|BIOS for T68KRC ​* }}
  
 CP/M-68K {{:​boards:​sbc:​tiny68k:​cpm15000.zip|CPM v1.3}} CP/M-68K {{:​boards:​sbc:​tiny68k:​cpm15000.zip|CPM v1.3}}
  
-CP/M-68K v1.3 distribution {{:​boards:​sbc:​tiny68k:​t68kram.zip|disk image}} ​ for Tiny68K ​RAMdrive+CP/M-68K v1.3 distribution {{:​boards:​sbc:​tiny68k:​t68kram.zip|disk image}} ​ for T68KRC ​RAMdrive
  
 {{:​boards:​sbc:​tiny68k:​console_rs232_interface.pdf|RS232 adapter}} ​ board to interface to the DB9 serial connector of a PC. The RS232 adapter is not needed for most USB-to-serial adapters which have TTL level I/O. {{:​boards:​sbc:​tiny68k:​console_rs232_interface.pdf|RS232 adapter}} ​ board to interface to the DB9 serial connector of a PC. The RS232 adapter is not needed for most USB-to-serial adapters which have TTL level I/O.
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 Utility Utility
  
-  * +  * Memory diagnostics 
- +  * Clear CP/M memory area
-Memory diagnostics +
- +
-  * +
- +
-{{:​boards:​sbc:​tiny68k:​clrcpmmem.zip|Clear CP/M memory}}  ​area+
  
 =====   ===== =====   =====
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 ==== Connect to a PC ==== ==== Connect to a PC ====
  
-A PC with terminal program such as Hyperterminal is needed to interface with Tiny68K. An USB-to-serial adapter with TTL level input/​output can connect directly to Tiny68K's console connector. For USB-to-serial adapter with RS232 I/O, an {{:​boards:​sbc:​tiny68k:​console_rs232_interface.pdf|adapter board }}  ​is needed.+A PC with terminal program such as Hyperterminal is needed to interface with Tiny68K. An USB-to-serial adapter with TTL level input/​output can connect directly to T68KRC's console connector. For USB-to-serial adapter with RS232 I/O, an adapter board is needed.
  
-==== Powering up Tiny68K ​====+==== Powering up T68KRC ​====
  
 Apply 5V to the board via the 2.5mm power jack, the center is 5V, barrel is ground. The nominal power consumption at 8MHz system clock is 500mA. When powered is applied, the 7-segment LED will display '​8'​ for a second and then '​6'​. While waiting for console command, the outer segments of the 7-segment display will flash for 1/2 second, one segment at a time, in a circular sequence. If the display indicate a static '​4',​ it is waiting for hardware handshake signal to assert. Be sure the terminal program has RTS/CTS hardware handshake enabled. Apply 5V to the board via the 2.5mm power jack, the center is 5V, barrel is ground. The nominal power consumption at 8MHz system clock is 500mA. When powered is applied, the 7-segment LED will display '​8'​ for a second and then '​6'​. While waiting for console command, the outer segments of the 7-segment display will flash for 1/2 second, one segment at a time, in a circular sequence. If the display indicate a static '​4',​ it is waiting for hardware handshake signal to assert. Be sure the terminal program has RTS/CTS hardware handshake enabled.
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 ==== Creating a new CF disk ==== ==== Creating a new CF disk ====
  
-Procedure for [[:​boards:​sbc:​tiny68k:​create_new_cf|creating a new CF disk]]+Procedure for creating a new CF disk
  
  
builderpages/plasmo/t68krc.1531541633.txt.gz · Last modified: 2018/07/14 00:13 by plasmo
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