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builderpages:plasmo:tinyz280:tinyz280_ec [2018/03/31 17:04]
plasmo
builderpages:plasmo:tinyz280:tinyz280_ec [2018/04/01 00:19] (current)
plasmo
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 The TinyZ280 {{:​builderpages:​plasmo:​tinyz280:​tinyz280_scm.pdf|schematic}} ​ contains annotated Engineering Changes. However, there are additional changes that are not described in the schematic. All the engineering changes are applied at the solder side of the TinyZ280 PC board. Below is the annotated photograph of the solder side. The TinyZ280 {{:​builderpages:​plasmo:​tinyz280:​tinyz280_scm.pdf|schematic}} ​ contains annotated Engineering Changes. However, there are additional changes that are not described in the schematic. All the engineering changes are applied at the solder side of the TinyZ280 PC board. Below is the annotated photograph of the solder side.
  
-{{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​builderpages/​plasmo/​tinyz280/​tinyz280_engineering_change_copy.jpg?​direct&​600x354|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_tinyz280_tinyz280_engineering_change_copy.jpg}}+[[https://​www.retrobrewcomputers.org/​lib/​exe/​fetch.php?​tok=f9e946&​media=https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​builderpages/​plasmo/​tinyz280/​tinyz280_engineering_change_copy.jpg|{{https://​www.retrobrewcomputers.org/​lib/​plugins/​ckgedit/​fckeditor/​userfiles/​image/​builderpages/​plasmo/​tinyz280/​tinyz280_engineering_change_copy.jpg?​direct&​600x354|www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_plasmo_tinyz280_tinyz280_engineering_change_copy.jpg}}]]
  
 Summary of the EC: Summary of the EC:
  
   * Extra ground wires and VCC wires are added to reduce the system noises.   * Extra ground wires and VCC wires are added to reduce the system noises.
-  * 923KHz clock to generate 57.7buad serial ​port +  * 12MHz divided by 13 to generate ​923KHz clock to counter1 input (Z280 pin 41).  The 923Khz clock is internally divided by 16 to generate 57.7buad serial ​clock. 
-  *+  * Z280 OPT input (pin 34) is pulled up to VCC 
 +  * nRDY2 and nRDY3 inputs (Z280 pin 63 and 58, respectively) are pulled to ground to enable the DMA channel 2 & 3. 
 +  * CPLD pin 33 is connect to RESET input of Z280.  This way Z280 is held in reset while CF is initialized. 
 +  * Mode jumper is connected to CPLD pin 34.  The jumper determines whether Z280 bootstrap using UART or CF.
  
  
builderpages/plasmo/tinyz280/tinyz280_ec.txt · Last modified: 2018/04/01 00:19 by plasmo
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