Engineering Change for adding PS2 interface to VGARC rev0.1

Introduction

This engineering change describe the pc board modifications, CPLD design changes, and software required for adding PS2 interface to VGARC rev0.1

Board modifications

To enable PS2 interface, test points T3 and T4 are connected to PS2 connector Data and Clock. Test points T5, T6, T7 are connected to data bus D[0], D[1], D[7].

Connections to PS2 connector

  • +5V (silkscreen '+') is connected to PS2 connector pin 4
  • Ground (silkscreen '-') is connected to PS2 connector pin 3
  • T3 is pulled up through a 4.7K resistor to +5V and connected to PS2 connector pin 1
  • T4 is pulled up through a 4.7K resistor to +5V and connected to PS2 connector pin 5

Connections to Data bus

  • T5 is connected to data bus D[0] (RC2014 connector pin 27)
  • T6 is connected to data bus D[1] (RC2014 connector pin 28)
  • T7 is connected to data bus D[7] (RC2014 connector pin 34)

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CPLD Changes

Here is the CPLD design file for VGARC with PS2 interface.

Schematic of the PS2 interface.

PS2 keyboard is access via bit banging I/O address 0xF4. There are 3 data bits on 0xF4 associated with PS2 keyboard. D[0] is PS2 Data, D[1] is PS2 enable, and D[7] is PS2 clock. At reset D[0] and D[7] are set to 1 (idle) while D[1] is set to low (disabled).

I/O address 0xF4 is readable and writable. Write only affect states of bit D[0], D[1], and D[7] while read captures the state of PS2 Data and PS2 Clock lines on D[0] and D[7], respectively. The keyboard interface is disabled at reset or by writing '0' to D[1] of the PS2 keyboard register. While disabled, PS2 Data and Clock are floating pulling up by 4.7K pull-up resistors. Writing '1' to D[1] of the PS2 keyboard register enables PS2 interface so the register contents of D[0] and D[7] are driven to PS2Data and PS2Clock, respectively.

Test Software

builderpages/plasmo/vgarc/ps2ec.txt · Last modified: 2020/11/30 07:51 by plasmo
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