Transputer Boards

This page is where I am documenting my rather long journey to develop a set of boards to support the INMOS Transputer. My objective is to build a significant sized machine of 32 or more CPU's with memory and some way to reconfigure the links. I also want to bring to life an ECB or S100 Link interface at some point so that it is possible to build from scratch a Transputer based system.

Transputer's a 5 second Introduction

A Transputer is a CPU originally designed by INMOS in the late 1980's. The CPU was designed with parallel computing in mind. Defining features of a Transputer are

  • 32bit CPU (T4xx/T8xx)
  • 4x 10/20Mbit/s serial links for communication to up to 4 other Transputers
  • Programmable in Occam, C, Pascal
  • Run O/S such as Minix and Helios

For more on the Transputer https://en.wikipedia.org/wiki/Transputer and also Axel Muhr's excellent site http://www.geekdot.com/hardware/transputer/

What is a TRAM

A TRAM is basically a standard carrier for an INMOS Transputer and the circuit for its function such as Compute with memory, SCSI, ethernet, serial etc. The following link provides some information regards the TRAM specification. http://www.transputer.net/tn/29/tn29.html#x1-50003.1

Example of TRAM can be seen plugged into the Tram Carrier Card below.

TRAM's are silly expensive on ebay! So probably not the place to start if you don't have any. Much better to wait for the ECB Transputer CPU Card.

Basic Transputer System

A basic Transputer system consists

  • Host - in this case the ECB based machine
  • Host Adapater Card or Transputer link Interface (see ECB Transputer Link Interface below)
  • Transputer Network - TRAM Carrier Boards or non-TRAM based CPU Cards (see ECB TRAM Carrier Card and Transputer CPU Card below)

the basic setup is

[Host CPU] <→ [BUS] <→ [Transputer Link Interface] <→ [Transputer Network]

The HOST CPU communicates to the Transputer network via the Transputer LInk Interface.

ECB Transputer Link Interface (aka TLI )

This is something I want to try and bring to the community as it will allow communication from an ECB system to a Transputer network.

It is slow progress and maybe one day I will hopefully finish the board design. I have started to design the link interface leveraging the prototype board work that is already in existence and borrowing heavily from Das Transputer Buch (yes that book really is a fantastic source of information).

The link interface would allow the connection of an ECB based system to a Transputer network. The ECB Tram Carrier Card is a candidate.

Mar/17 - Design almost finalised, just need to complete the bus connections before sending to PCBWay (http://www.pcbway.com/) for the first run.

ECB TRAM Carrier Card (aka 4TC2 )

The idea here is to create a simple ECB card that can support 1-4 INMOS TRAM's. Have started work but original design needs some revision to make it more aligned with standard practices.

Have finalised a design

  • Supports 4 TRAM's
  • cascade to multiple boards
  • Power from EuroConnector or external standalone
  • Breakout for all unused links

I sent the files to PCBway (http://www.pcbway.com/) for manufacture. Once tested will put this up in the ECB boards section with all the right gerber files.

Gerber files for version 0.4 of the board :builderpages:trick-1:4tc2v0.4.zip

Jan/17 - Boards arrived from PCBway, well packed, professionally made and in cool red! Have assembled and tested 1 unit. Some minor layout, screen print and design issues to resolve but they work!

4tc2_0.4_bare.jpg

Feb/17 - Version 0.4 of the board is now confirmed fully working however a number of design modifications have been made and Version 0.5 of the board is pending.

4tc2_0.4_1tram.jpg

v0.4 plugged into Axel @ Geekdot's Apple II Transputer Link Card

4tc2-aii.jpg

Proof of life. Simple BASIC program using PEEK/POKE to interact and confirm that there is a Transputer connected.

atc2-alive.jpg

The following is the image of the version 0.4 board with 4 INMOS TRAM's installed.

4tc2.jpg

Jul/17 - Version 0.5 of the board has been finalised and sent for manufacture (http://www.pcbway.com).

Jul/17 - Version 0.5 boards have arrived.

4tc2_0.5_bare.jpg

The following files are what have been sent. Please note that this version has had some modifications and re-routing from v0.4 of the board and as yet have not been tested.

  • Schematic :builderpages:trick-1:ecb_tram_carrier.pdf
  • Gerber Files :builderpages:trick-1:4tc2v0.5.zip

ECB Transputer CPU Card (TCPU)

This card is in initial design phase but is aiming to be

  • 1-2x Transputer CPUs on board
  • Minimum 1MB SRAM
  • head and tail connector
  • breakout of unused links
  • Power from EuroConnector or external for standalone

This is ideal for those who want to put a Transputer in their system but maybe cannot get hold of a TRAM module.

ECB Transputer CPU Card -TCPUv0.1

6/7/2017 Have decided that the first development version will be just the Transputer, link connections, power and mandatory support circuit all other pins from the Transputer will be broken out into a header so that I can experiment with memory and other peripherals.

KiCAD and Gerber Files :builderpages:trick-1:ecbtcpu_version_0.1.zip

7/7/2017 Version 0.1 files have been sent to manufacture at (http://www.pcbway.com)…

Jul/17 0.1 boards have arrived….

ecb_t-cpu.jpg

Sep/17 Version 0.1 board finally built, tested and working!.

errata so far

  • Error should have been presented as notError - need to add a 74LS04 inverter to the next version of the board
  • Link0 not presented in the uplink header. Link3 is there instead.
  • Link Speed Jumpers need to be added
  • Tidy up link locations and label

The following shows the current state. You can see the 74LS04 on a vero board behind the main board. Also the brown wire jumper down to the breakout where the link speed connections ended up. Plugged into my IIe running the basic test code and those magic words “32 BIT TRANSPUTER FOUND”

ecbtran0.1.jpg

next step is to build out some memory options

ECB Transputer CPU Card -TCPUv0.2

In planning but will be looking to fix the errors of version 0.1 and add the first go at memory.

Also considering adding the bus to link interface circuit so that the board will work standalone in an ECB system but that might wait until version 0.3

Version 0.2 of the TCPU board arrived late December and as usual I got caught up in other things. Building this simple board was been slow progress and was finished in late February. Unfortunately the memory didn't turn up for another month….

Here is the blank board.

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Here is the board finally completed and connected to the PC for testing.

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Initial tests failed to the CPU, after a while I realised I had tied one of the control lines (Analyze) to ground for some mad reason when I was re-drawing a section of the schematic, out with the knife and some bodging later I was able to see the Transputer. However I could not find any memory. About two months worth of frustration later I have finally managed to identify and talk to the memory, although not reliably or quickly. The issues:

  • I had forgotton to connect notMemS0 to the 74F373 enable pin
  • I had used a KiCAD 2×10 IDC connector in the schematic that numbers down one side and then up the other, on the board layout I selected one that goes from left to right and down in the numbering…..end result memory timing and configuration jumpers were not where I expected. Took a while to work that out.

The following shows the current test setup

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Any how as of late May I am now getting the following which shows that it is at least identifying the memory. However it is not talking to it reliably.

www.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_trick-1_img_8126.jpgwww.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_trick-1_img_8129.jpgwww.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_trick-1_img_8131.jpgwww.retrobrewcomputers.org_lib_plugins_ckgedit_fckeditor_userfiles_image_builderpages_trick-1_img_8132.jpg

(sorry they are on an angle)

As can be seen lots of errors and lots of different memory sizes for Transputer number 9 which is the one that we are testing. off to read more manuals and recall all that I have lost about T states :-)

The Transputer CPUs (T4xx/T8xx) have a programmable three-cycle memory interface. Through jumper configurations on the board they can support a variety of DRAM and SRAM. More information can be found in the reference manual http://www.transputer.net/ibooks/72-trn-203-02/tdata3rd.pdf .I am now working through the various combinations to determine the best configuration for the memory I am using as the it is not being reliably identified.

I am also yet to get the bank 1 operating. I will do this once I get bank 0 working properly.

So there we have it - some progress.

Next iteration I am going to

  • fix the above issues
  • remove the ECB bus connector as I have decided a) I need the real estate b) it is a wast of a connector just for power c) power comes through the link interface.

TCPU v0.3 and 0.4

August 2019

So its been a couple of years, work and life have got in the way. Version 0.3 was a total dud….so lets move straight onto v0.4

Per the last update I have removed the ECB connector. I also settled on ZIP memory TC514400AZ's ( https://datasheetspdf.com/pdf-file/1091701/Toshiba/TC514400AZ-60/1 ).

The result is that I now have a Trransputer 4Mbytes of memory working (happy day!) The 0.4 board is not without issues so needs a bit of TLC. The GND somehow didn't connect to the memory. Also the AD11 on the memory didn't get connected to the bus. Lots of head scratching on that one with various errors. I am also going to move some of the resistors closer to the 74ACT86 and remove some of the jumpers that just aren't needed.

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output from ispy | mtest -x

The last line of the last command run is “proof of life”

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Now the command doesn't return consistently but I think that is power…to be confirmed. For now thought it is working :-)

TCPU v0.5 and 0.6

So this iteration I have taken the plunge and refactored the schematic, with fixes, from v0.4 to a Size 2 TRAM. The board is a 4 layer board (Signal, GND, Signal, Signal). Version 0.5 for some bazar reason had an issue with some pinouts on the TRAM connector but basically is functional. v0.6 is currently being manufactured and will fix this issue. Once complete and tested I will make this available.

The following are photos of the v0.5 board.

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ECB Manual Cross Bar Switch (MCBS)

This card has been designed but is yet to be manufactured for testing. This is mainly because I have not built enough ECB based Transputer cards to warrant doing so. In theory it is a manual version of the INMOS IMSC004 Cross Bar Switch. Obviously not software configurable.

The card allows the connection of all unused links from other ECB Transputer boards via a single ribbon cable and then allow for the link configuration to be set with jumper cables. This will allow for maximum configuration of a given set of Transputers cards from either Final version of TCPU or 4TC2v0.5 and above.

The following are the KiCAD Design and Gerber Files. I have never had this board fabricated but as you can see it is rather simple.

KiCAD :builderpages:trick-1:ecb_crosspatch_20170706.zip

Gerber :builderpages:trick-1:ecbtcrosspatch.zip

builderpages/trick-1/transputers.txt · Last modified: 2019/11/15 19:40 by trick-1
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