Multicomp playground

If you started your Multicomp journey with Grante Searle's web page, then you would have started with one or more AS6C1008 chips. If you progressed from the original point to point soldering setup to the Multicomp PCB you will now find yourself with a PCB capable of supporting two RAM chips.

However, the Multicomp IIc does not support 2 x 128kb chips. It is designed to use the following memory options:

  • 1 x 128kb RAM (AS6C1008) ; or
  • 1 x 512kb RAM (AS6C4008); or
  • 2 x 512kb RAM (2xAS6C4008).

The following documentation describes my effort to configure the Multicomp to access the two 128Kb RAM chips as a contiguous block of 256Kb.

The memory configuration on the Multicomp is controlled by a set of three jumpers and these configure the connections to pin 1, 2 and 30 on RAM chip one.

  • A16 Jumper
  • A17 Jumper
  • A18 Jumper

These jumpers only affect the configuration of RAM chip one. RAM chip two has all address lines connected directly to the FPGA.

The limitation with using 128Kb chips is that that A17 and A18 address line connections on the chip perform different functions on the 128Kb chip:

  • A17 is a secondary chip enable.
  • A18 is not connected.

So, if you have two 128Kb chips, the Multicomp will not recognize the second chip and configure it as a contiguous block.

How to use 2x128Kb chips of your Multicomp IIc.

Code changes required:

In the CycloneIIc.vhd file make these two changes:

1) Under Cyclone IIc entity add:

   CHIPOE        : out std_logic:='1';


n_externalRam1CS<= not(n_monRomCS and not physicaladdr(19));
n_externalRam2CS<= not(n_monRomCS and physicaladdr(19));


n_externalRam1CS<= not(n_monRomCS and not physicaladdr(17));
n_externalRam2CS<= not(n_monRomCS and physicaladdr(17));

Make the following two change to the pin configurations using the Pin Assignment Editor:

1) Disable the A17 address line output to PIN_31

2) Create a new output CHIPOE to drive PIN_31 high permanently.

Configure the Jumpers:

A162-3Connect FGPA pin 25 address line A16 to pin 2 of RAM chip one which is the chips A16 address line.
A172-3Connect FPGA pin 31 which is the new CHIPOE high signal to RAM chip one pin 30 which is the secondary chip enable.
A182-3Connect FPGA pin 32 address line A18 to pin 1 of RAM chip one which is an unused pin.


After these three sets of changes have been done, recompile and program your Multicomp.

I have tested this configuration using the Debug Monitor by writing to different banks and the chip enable and mapping appears to work correctly.

What this gives you:

  • An address range 0-0x40000 which the MMU sees as a contiguous block mapped as 16 x 16kb blocks 0 - 15.
  • Under the Debug Monitor 5 banks of 48Kb mapped across that range:
    • Bank 0 - block 0, 1, 2 + 3 (common block - Debug Monitor)
    • Bank 1 - block 4, 5, 6 + 3 (common block - Debug Monitor)
    • Bank 2 - block 7, 8, 9 + 3 (common block - Debug Monitor)
    • Bank 3 - block 10, 11, 12 + 3 (common block - Debug Monitor)
    • Bank 4 - block 13, 14, 15 + 3 (common block - Debug Monitor)

The remaining limitation is the CP/M, CP/M 3 and MP/M software is unable to dynamically recognize this memory configuration.

Thanks to the assistance of Max Scane and Rienk and of course Grant Searle for his original work.

Configuring CP/M 2.2 to use 2 x 128Kb RAM chips.

CPM 2.2 uses only 64Kb for executing programs so the remainder of the RAM can be set up as a 192Kb RAM disk. Rienk has already done all the groundwork here with his CPM package. Rienk's package is designed for 512Kb and 1024Kb systems and he has cleverly designed multiple systems to share the RAM disk. As CP/M 3 requires an 128Kb base his design configures the RAM disk to start after 128Kb. For my purposes, I am only using CP/M 2.2 so this configuration will be removed.

The components of this package that need to be considered are:

BOOT ROMThe boot rom does not contain any RAM banking code that requires modification.
CBIOS217.ASMThe disk parameter table for the memory disk needs to be updated for the smaller memory size and the memory size detection code needs to be disabled. The start point needs to be adjusted to start at 64Kb.
CPM22.ASMDoes not contain any RAM banking code that requires modification.
RDINIT.COMThe ram disk initialization program needs to be updated for the RAM disk to start at 64Kb.

Changes required to CBIOS217.ASM

Update the Memory offset to skip 64Kb rather than 128Kb

MOFF        equ 4    ; reserved tracks

Update the disk parameter block for 192Kb RAM disk.

dpbM:    ; 192 kB Memory disk
    dw 128        ; SPT - sectors per track (16 kbyte memory block)
    db 4        ; BSH - block shift factor
    db 15        ; BLM - block mask
    db 1        ; EXM - Extent mask
    dw 95        ; DSM - Storage size (blocks - 1)
    dw 127        ; DRM - Number of directory entries -
    db 11000000B    ; AL0 - 1 bit set per directory block
    db 0        ; AL1 -            "
    dw 0        ; CKS - DIR check vector size (DRM+1)/4 (0=fixed disk)
    dw MOFF        ; OFF - Reserved tracks; tracks first 64 k is system RAM

Disable the memory detection code (now hard coded for 256Kb).

; test SRAM size
;    ld A,1
;    out (MMU_SEL),A
;    ld A,32            ; address second SRAM chip
;    out (MMU_FRM),A
;    ld HL,4100h        ; arbitrary address
;    ld (HL),A        ; write something
;    cp (HL)            ; read it back
;    jr Z,sizeOK        ; if the same, second SRAM is present
;    ld A,0BFh        ; if not, modify dpbM
;    ld (dpbM+5),A        ; DSM = 191
;    xor A
;    ld (dpbM+6),A
;    inc A
;    ld (dpbM+4),A        ; EXM = 1
;sizeOK:    ld A,1
;    out (MMU_SEL),A        ; restore system memory
;    out (MMU_FRM),A

Once these changes are done, assemble the file with PASMO and update the final HEX line as described in the 1_BIOS\Buildit.txt

Then proceed through the CP/M install process as described in the INSTALL.TXT file including loading the CPM22FilesPkg.

At this point the RAM disk is not initialized. We need to modify the RDINIT.COM file to setup the directory structure after the 64Kb.

One way to do this is to patch the existing RDINIT.COM file. You could also modify, assemble and download a new version of the RDINIT file.

The key change we need to make is to change the instruction:

011F LD A,08


011F LD A,04

We do this by:

  1. Loading the RDINIT.COM into memory with ZSID.
  2. Changing the start memory page point.
  3. Moving the change file to upper memory.
  4. Saving the changed program to disk.
  5. Executing the new program.
  6. Reset the drive.


011f LD A,04

0121 .



A>save 1

RamDisk: Initialized
A>stat dsk:

    A: Drive Characteristics
65408: 128 Byte Record Capacity
 8176: Kilobyte Drive  Capacity
  512: 32  Byte Directory Entries
    0: Checked  Directory Entries
  256: Records/ Extent
   32: Records/ Block
  128: Sectors/ Track
    1: Reserved Tracks

    M: Drive Characteristics
 1536: 128 Byte Record Capacity
  192: Kilobyte Drive  Capacity
  128: 32  Byte Directory Entries
    0: Checked  Directory Entries
  256: Records/ Extent
   16: Records/ Block
  128: Sectors/ Track
    4: Reserved Tracks

A>stat m:
Bytes Remaining On M: 188k


64kb base memory + 4Kb directory + 188Kb disk space = 256Kb

Use a microSD adapter for and SD socket on your Multicomp.

If you are unable to obtain an SD card socket or locate the correct size socket for your Multicomp then you can use a microSD adapter:

playground/b1ackmai1er/start.txt · Last modified: 2017/12/30 00:25 by b1ackmai1er
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