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Project Oberon [message #116]

Wed, 09 December 2015 12:57

nealcrook
Messages: 127
Registered: October 2015
Location: UK

Senior Member

Oberon is a programming language developed by (amongst others) Nicklaus Wirth, of Pascal and Modula2 fame.

In the 1980s, ETH in Zurich built a workstation "Ceres" to run Oberon, the OS, implemented in Oberon, the language (the preface to "Programming In Oberon" states that they were inspired by a visit to Xerox.. I think the Xerox workstation OS was coded in BCPL.)

There is now a Oberon RISC CPU to run the OS. There is a Verilog implementation and an (out of stock) Xilinx-based FPGA board to run it on.

If that whetted your appetite, more here:

http://www.projectoberon.com/

Oberon is from the 80's, so it must be "retro"...

Neal.

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Re: Project Oberon [message #117 is a reply to message #116]

Wed, 09 December 2015 13:19

Andrew B
Messages: 467
Registered: October 2015
Location: Near Redmond, WA

Senior Member
Administrator

This is really neat.

I always intended that the "RetroBrew" name would be an "OR" of Retro and Homebrew and not an "AND", so this definitely fits.

I think maybe we should make a "links" page on the Wiki for things that aren't their own board design on the RBC site, but might be interesting to users. Things like Grant S's Multicomp, this project, Oscar V' PiDP-8 replica, the guy who built the wire-wrapped Apollo Guidance Computer (I really really really really want to build an AGC someday, but on PCBs)...

[Updated on: Wed, 09 December 2015 13:20]

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Re: Project Oberon [message #161 is a reply to message #117]

Sun, 13 December 2015 21:39

dylanmc
Messages: 1
Registered: October 2015

Junior Member

Here is a great (recent!) video from Dr. Wirth about this work, and his career:

(can't post links yet - Google for "Reviving a computer system of 25 years ago Wirth"

A highlight: he's planning on re-releasing the Oberon book, with a modernized CPU implemented in FPGA. He's still an amazing gentleman.

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Re: Project Oberon [message #162 is a reply to message #161]

Sun, 13 December 2015 22:32

Andrew B
Messages: 467
Registered: October 2015
Location: Near Redmond, WA

Senior Member
Administrator

https://www.youtube.com/watch?v=EXY78gPMvl0

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Re: Project Oberon [message #165 is a reply to message #162]

Sun, 13 December 2015 22:54

Andrew B
Messages: 467
Registered: October 2015
Location: Near Redmond, WA

Senior Member
Administrator

Lots of Spartan-3 development boards on eBay these days, down to $35 - http://www.ebay.com/itm/XC3S500E-XILINX-Spartan-3E-FPGA-Eval uation-Development-Core-Board-XCF04S-FLASH-/261136644066?has h=item3cccf4f7e2:m:moTYIhWh6OyQtJEn4k7GZ4A

I feel like we should do an RBC "host board" for the Spartan, similar to the Multicomp host boards for the Cyclone II, and get this up and running again!

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Re: Project Oberon [message #243 is a reply to message #165]

Tue, 05 January 2016 22:58

Andrew B
Messages: 467
Registered: October 2015
Location: Near Redmond, WA

Senior Member
Administrator

I spent some time downloading the Altera Cyclone II/IV Quartus software and importing the Project Oberon Verilog files into it.

The files use some Xilinix-specific primitives to define the clock generation and tri-state buffer groups on the overall top level file.

If we could alter the Verilog slightly to compile on an Altera board, then maybe we could get Oberon to run on the Cyclone II or Cyclone IV boards that we already have member experience with from the Multicomp project?

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Re: Project Oberon [message #245 is a reply to message #243]

Wed, 06 January 2016 05:24

nealcrook
Messages: 127
Registered: October 2015
Location: UK

Senior Member

Andrew,
this does sound like a cool project. I don't know how much experience you have of Verilog and/or FPGAs but I'd recommend doing whatever set of hacks is needed to get the code to compile and map, so that you can get through to the fitter and see whether there is any chance of squeezing it on to one of the Cyclone parts.

Regarding the clocking, anything involving PLLs or special routing resources tends to be very FPGA-family specific. I suggest creating a module that matches the ports of the Xilinx primitive and within it just wiring all the output clocks to input clock, so that you end up with a single clock domain. This won't *function* but it will give the tools the best chance and you can incrementally refine this once you have a degree of confidence that it will fit.

Regarding the tri-state control, in the multicomp VHDL the tristate control is coded by assigning a Z onto the bidirect signal associated with a primary I/O pin; the tools then magically takes care of the real control. That same approach might work here (either by recoding the existing stuff or by creating a module that matches the Xilinx primitive and coding it there.

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Re: Project Oberon [message #247 is a reply to message #243]

Wed, 06 January 2016 13:34

yoda
Messages: 125
Registered: October 2015
Location: Cedar Rapids, IA

Senior Member

There will be some alterations required other than the ones you mentioned but should not be too hard I think. The SRAM access will have to be changed as the Xilinx board and the paper on the code point out is 512K x 16 and the multi comp board uses 8 bit wide SRAM and also would be half as large. I don't know if only having 1MB on multi comp vs 2MB on the Xilinx board will make a difference - need to also check if all the memory was used. I seem to recall a mention of 1Meg program space and the extra memory was used as frame buffer for display. If that is true it may be a problem with current multi comp SRAM configuration.

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Re: Project Oberon [message #8095 is a reply to message #247]

Tue, 17 November 2020 03:25

tingo
Messages: 115
Registered: February 2017
Location: Oslo, Norway

Senior Member

FWIW, Oberon now runs on the ULX3S board.
https://github.com/emard/oberon
Current implementation is the same as Project Oberon 2013; 1 Megabyte RAM.
It might be possible to get Oberon working on a Multicomp board.

Torfinn

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Re: Project Oberon [message #8129 is a reply to message #8095]

Thu, 10 December 2020 11:04

tingo
Messages: 115
Registered: February 2017
Location: Oslo, Norway

Senior Member

Currenty trying to figure out a way to make the Multicomp memory appear the way Project Oberon wants it. The RISC5 cpu wants a 32-bit wide memory, but (as has been pointed out earlier in this thread) a few implementations have 16-bit physical memory.

Torfinn

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Re: Project Oberon [message #8130 is a reply to message #8129]

Thu, 10 December 2020 12:10

kman
Messages: 45
Registered: February 2019
Location: Germany

Member

QMTech has some very nice FPGA core boards with ALTERA or XILINX FPGA on it. ALTERA-FPGA size is 15k , 23k and 55k LE, XILINX-FPGA is 16k LE (or what every they call it ;-) Wink

. Some links:

CycloneIV EP4CE15 w. SDRAM 16Mx16
CycloneIV EP4CE55 w. SDRAM 16Mx16
CycloneV 5CEFA2F23 w. SDRAM 16Mx16
XILINX XC6SLX16 Spartan-6 w. DDR3 256MB

All core boards have 2x64 pin header 2.54mm and identical IO and power pinning, so they are exchangable, the IO-naming is different !. I use the ALTERA EP4CE15 core board on my multicomp PCB. May be its a option as a starting point. If you drop the JoyIO-Board there is a 32 IO Pin-header w. +5V and 3V3 for hardware expansion and some other interface connectors.

Cheers
Kurt

[Updated on: Thu, 10 December 2020 12:12]

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Re: Project Oberon [message #8132 is a reply to message #8130]

Fri, 11 December 2020 10:18

tingo
Messages: 115
Registered: February 2017
Location: Oslo, Norway

Senior Member

Well, for me the interesting challenge is to see if I can get Oberon working on a board I already have, not to get more FPGA boards. Smile

muellerk wrote on Thu, 10 December 2020 21:10

I use the ALTERA EP4CE15 core board on my multicomp PCB.

Nice and interesting board! Have you ported anything interesting to it?

Torfinn

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Re: Project Oberon [message #8133 is a reply to message #8132]

Fri, 11 December 2020 19:23

kman
Messages: 45
Registered: February 2019
Location: Germany

Member

Quote:

[...]not to get more FPGA boards

I agree, it's a good idea to use a fpga board from our forum wiki, that keeps the inflation of pcb's for each new project small.

Quote:

Nice and interesting board! Have you ported anything interesting to it?

superfluous question, if you want to use a 32-bit processor for your oberon project the used resources should be sufficient. My suggestion focuses on the QMTECH EP4CE15 core board not on my pcb, its only the carrier for the QMTECH board. My personal challange was to add some interresting hardware in VHDL to the multicomp idea incl. the needed interface connectors (= my PCB). So our goals are different, but there might be some synergies.

Cheers
Kurt

[Updated on: Fri, 11 December 2020 19:23]

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