Parent: ECB 4PIO

File: Thu Apr 7 16:59:04 2011 DSC_0094.jpg (709654 bytes)
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File: Fri Apr 8 15:53:25 2011 addressing logic trace 20H.tiff (1947782 bytes)
Douglas W. Goodall at 4:08 pm on Apr 8, 2011:

This is a logic trace of the 4PIO PIO-0 being accessed with an "in 20" from ddt.

When the address 20H is asserted on the address lines, and the dip switch is set properly for the default configuration AB4=ON, AB5=OFF,AB6=ON,AB7=ON, the output of IC5 (74LS85) Oa=b pin 6 is HIGH and is presented to IC7A (74LS139) A0 pin 2. IC7A A1 is wired to /ORQ. When those two conditions are satisfied, the active low signal from IC7A O1 pin 5 is sent on to IC78 for further discrimination where AB2 & AB3 are decoded to select the specific PIO being addressed. The result of this is that one only chip select will be output from IC7B, In the case of an access to port 20H, it would be IC7B O0 pin 12 for /CE-PIO0. My thanks to Wolfgang Kabatzke for answering my questions about this.

File: Thu Apr 7 16:59:05 2011 ecb-4pio-600dpi.jpeg (2607830 bytes)