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boards:sbc:sbc_v2:start [2019/06/19 09:07] b1ackmai1er [Speed switch modification:] |
boards:sbc:sbc_v2:start [2020/12/02 08:39] (current) b1ackmai1er [SBC V2] |
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The SBC V2 is a Zilog Z80 processor board. It's a 100x160mm board that is capable of functioning both as a standalone SBC or as attached to the ECB bus. | The SBC V2 is a Zilog Z80 processor board. It's a 100x160mm board that is capable of functioning both as a standalone SBC or as attached to the ECB bus. | ||
- | ===== Features ===== | + | Previously known as the N8VEM SBC, development began in 2006 wth V1 and is currently still in development. |
- | * 4Mhz Zilog Z80 CPU | + | For most people, the [[: |
- | * Up to 512Kb paged SRAM. | + | |
- | * Up to 1Mb EPROM or FLASH ROM. | + | |
- | * Serial Interface (16550 Uart) | + | |
- | * Parallel interface (8255), can be extended to support IDE interface via small board | + | |
- | * Real Time Clock (DS1302) | + | |
- | * Battery backup for RTC and SRAM. | + | |
- | * Standard ECB bus interface | + | |
- | * Standard PC drive connector power supply interface using +5V only | + | |
- | * Reset button with external connector | + | |
- | * Status LED | + | |
- | ===== Software Support ===== | + | |{{https:// |
+ | |[[: | ||
- | * ROMWBW BIOS featuring | + | \\ |
- | * CP/M / ZSDOS | + | |
- | * RAM & ROM disk support. | + | |
- | * ROM based BASIC, FORTH and Monitor. | + | |
- | ===== Pictures | + | ===== Features |
- | {{https:// | + | * 4Mhz+ Zilog Z80 CPU. |
+ | * Up to 512Kb paged SRAM. | ||
+ | * Up to 1Mb EPROM or 512Kb Flash ROM. | ||
+ | * Serial Interface. | ||
+ | * IDE interface. | ||
+ | * Real Time Clock. | ||
+ | * Onboard sound. | ||
+ | * Battery backup for RTC and SRAM via super capacitor. | ||
+ | * Standard ECB bus interface. | ||
+ | * +5V power connector for Single Board Computer operation. | ||
+ | * Reset button. | ||
+ | * Status LED. | ||
- | [[: | ||
+ | ===== Software Support ===== | ||
- | ===== Board ===== | + | [[: |
- | A description of the circuit operation can been seen here: [[http://obsolescence.wixsite.com/ | + | * CP/M / ZSDOS |
+ | * RAM & ROM disk support. | ||
+ | * ROM based BASIC, FORTH and Monitor. | ||
+ | * Prebuild disk images | ||
- | The current version is SBC-V2-003A. A new version is under development and details can be found [[:boards: | + | ROMWBW Eurocard expansion board driver support: |
- | Schematics: {{: | + | * RAMFLOPPY |
+ | * VDU | ||
+ | * CVDU | ||
+ | * VGA3 | ||
+ | * Zilog Peripherals | ||
+ | * USB FIFO | ||
+ | * Disk I/O | ||
+ | * 4PIO | ||
+ | * SCG | ||
+ | * DSKY | ||
+ | * DUAL SD CARD | ||
+ | * MF-PIC | ||
- | PCB Board: {{: | ||
- | Gerbers: {{: | + | ====== Version History ====== |
- | Kicad: {{: | + | ^Version^Details^Key feature| |
- | + | |[[: | |
- | {{https:// | + | |[[: |
- | + | |[[:boards:sbc:sbc_v2: | |
- | + | |[[:boards:sbc:sbc_v2: | |
- | ===== Jumper Settings ===== | + | |
- | + | ||
- | The following table outlines the correct jumper settings for the SBC V2 board: | + | |
- | + | ||
- | ^Board Reference^Jumper Description^ | + | |
- | | | + | |
- | |JP2|One bit input port|X| | + | |
- | |K1|U2 EPROM chip pins (32-pin or 28-pin)|X *| | + | |
- | | | + | |
- | |K2|UART side hardware handshaking (DSR, CTS)|X *| |DSR (this should be paired with K3 - DTR) - default| | + | |
- | | | + | |
- | |K3|UART side hardware handshaking (DTR, RTS)|X *| |DTR (this should be paired with K2 - DSR) - default| | + | |
- | | | + | |
- | |K4|Serial side hardware handshaking (DSR, CTS)|X *| |DSR (this should be paired with K5 - DTR) - default| | + | |
- | | | + | |
- | |K5|Serial side hardware handshaking (DTR, RTS)|X *| |DTR (this should be paired with K4 - DSR) - default| | + | |
- | | | + | |
- | |K6|U2 chip type (27C080 EPROM, 29C040 flash)|X *| | + | |
- | | | + | |
- | |K7|U23 SRAM (512K or 128K)|X *| |512K chip used in U23 - default| | + | |
- | | | + | |
- | |K8|U2 chip type (27C080 EPROM, 29C040 flash)|X *| | + | |
- | | | + | |
- | |K9|Parallel Port power control (pin 25)|X *| | + | |
- | | | + | |
- | |K10|MCPL (Memory Page Config Latched)|X *| |32K upper RAM fixed/32K lower RAM switchable memory map - default| | + | |
- | | | + | |
- | |K11|MCPL (Memory Page Config Latched)|X *| |32K upper RAM fixed/32K lower RAM switchable memory map - default| | + | |
- | | | + | |
- | |K12|Bus Interrupt (pin A23)|X *| | + | |
- | | | + | |
- | |K13|ECB/ | + | |
- | | | + | |
- | + | ||
- | * = default setting | + | |
- | + | ||
- | ===== Serial Cable Instructions ===== | + | |
- | + | ||
- | The SBC V2 doesn' | + | |
- | + | ||
- | First, you must build a cable with an IDC-10 plug on one end (plastic rectangular connector with 2 rows of 5 pins) and a female DE-9 plug (ie. a serial port plug) on the other end. | + | |
- | + | ||
- | The female DE-9 plug is what you will plug into the serial port of your host computer. Serial ports (on the back of the computer) are male ports (ie. they have pins), so the plug at the end of this cable must be a female plug (they have holes). It's not recommended to use accessory serial cables to make this connection (such as null modem cables, etc.). This is because many such cables are wired for specific applications, | + | |
- | + | ||
- | The following cable layout shows what is being connected where in this cable: | + | |
- | + | ||
- | ^IDC-10 side^DE-9 side| | + | |
- | |2|4| | + | |
- | |3|3| | + | |
- | |5|2| | + | |
- | |7|6| | + | |
- | |9|5| | + | |
- | + | ||
- | Pin 1 on the IDC plug is marked with an embossed triangle on the plug, and this pin corresponds to pin 1 on the pcb which is marked with a square solder hole (at the lower-right most position of the plug on the SBC V2 pcb). The pins on the DE-9 plug are usually marked right on the plug itself in tiny numbers. Strip some wires and solder away. Instead of stripping wires and soldering manually, you can also use ribbon cable and special " | + | |
- | + | ||
- | Always double and triple check where you’re soldering something before you solder it. When you’ve built your cable, use your multimeter to check connectivity between each pin on the IDC-10 side and the DE-9 side according to the arrangement above to make sure you got it right. | + | |
- | + | ||
- | In order to test connections in a plug you cannot stick the multimeter lead into the hole (because it will not fit). Instead, take a spare piece of wire, stick it into the hole for the pin you want to test, and then touch the multimeter lead to that wire. | + | |
- | + | ||
- | ==== Flow control considerations: | + | |
- | + | ||
- | ROMWBW will automatically identify the type of serial chip installed. Depending on the capability of the serial chip, flow control may or may not be available. Chip data sheets cannot be relied upon to accurately identify the chips capability. | + | |
- | + | ||
- | In the absence of flow control, guidelines for baud rate settings are: | + | |
- | + | ||
- | 4Mhz CPU Crystal - 38400 baud | + | |
- | + | ||
- | 8Mhz CPU Crystal - 57600 baud | + | |
- | + | ||
- | Baud rate can be changed using the CP/M MODE program i.e. [[: | + | |
- | + | ||
- | If garbled characters are seen on the display or serial file transfers fail, a lower baud rate should be tried. | + | |
- | + | ||
- | + | ||
- | ===== Parts List ===== | + | |
- | + | ||
- | Full list of parts:{{: | + | |
- | + | ||
- | See [[: | + | |
- | + | ||
- | ===== Software ===== | + | |
- | + | ||
- | There is extensive firmware support for the SBC V2 and associated ECB peripheral cards. Currently there are two firmware builds still being actively developed | + | |
- | + | ||
- | See [[: | + | |
- | + | ||
- | A debug boot ROM can be installed for testing - try James Moxham' | + | |
- | + | ||
- | [[https:// | + | |
- | + | ||
- | ==== REAL TIME CLOCK (RTC) ==== | + | |
- | + | ||
- | The DS1302 real time clock can be set under CP/M using the **rtc** utility program. | + | |
- | < | + | |
- | Loading CPM... | + | |
- | CP/M-80 Version 2.2C for the N8VEM, October 2008 | + | |
- | Run XM from A drive, this downloads file to B drive | + | |
- | A>rtc | + | |
- | Start RTC Program | + | |
- | RTC: Version 1.0 | + | |
- | RTC: Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut H)elp | + | |
- | RTC: trickle charger disabled. | + | |
- | RTC> | + | |
- | </ | + | |
- | + | ||
- | Set the time and date with the** //Init// **command first and then use the // | + | |
- | + | ||
- | RTC.COM can also be used to set up trickle charging for the backup battery or super capacitor if connected. More Information on charging Super Capacitors can be found here: [[https:// | + | |
- | + | ||
- | The utility can also set and read the RTC memory. | + | |
- | + | ||
- | [[: | + | |
- | + | ||
- | + | ||
- | ===== Status LED ===== | + | |
- | + | ||
- | A single color or bicolor LED can be installed for the status LED. The LED monitors the status of the HALT line from the Z80 CPU. Consider the color selection and orientation when choosing. A red/green LED is ideal and logically should show green when cpu is running and red when halted. Or in the case of a single colour LED, on when cpu is running and off when halted. It is wise to not fully solder in the LED until the orientation has been checked to confirm the right sequence. Or, you could install a pin header and run flying leads to an LED mounted in a case, | + | |
- | + | ||
- | The HALT status can be initiated by booting CP/M and running the DDTZ debugger, loading and executing a HALT instruction. | + | |
- | + | ||
- | < | + | |
- | B>ddtz | + | |
- | DDTZ v2.7M by CB Falconer. CPU=Z80 | + | |
- | -a100 | + | |
- | 0100 hlt | + | |
- | 0101 | + | |
- | -g100 | + | |
- | </ | + | |
- | + | ||
- | ===== Memory Paging ===== | + | |
- | + | ||
- | The SBC can be configured with 128Kb or 512Kb RAM and up to 512Kb ROM. The Z80 processor can only access 64Kb at one time, so the additionally memory is accessed through a memory paging scheme. | + | |
- | + | ||
- | The memory paging system can be configured in two different ways but the default is to be set with 32Kb of RAM fixed at the top 8000h-FFFFh memory range and for the bottom 32Kb 0000h-7FFFh being selectable from either the RAM or ROM chips. This 32Kb/32Kb configuration is what is supported by the ROMWBW software package. | + | |
- | + | ||
- | Under the 32Kb/32Kb configuration, | + | |
- | + | ||
- | + | ||
- | ===== One Bit Input Port ===== | + | |
- | + | ||
- | Bit 6 of RTC port $70 is connect to an on board jumper JP2 which can be read by software. By default it is tied high. Removing jumper JP2 will result in the being tied low (=0). | + | |
- | + | ||
- | Effectively this creates a configurable jumper setting which the ROMWBW bootrom can use for determining the primary communications console. | + | |
- | + | ||
- | This facility is not enabled by default in ROMWBW and the setting is ignored. To enable, rebuild the ROMWBW package with the CRTACT setting set to true. The CRT type can also be configured at this time: | + | |
- | + | ||
- | <font inherit/ | + | |
- | + | ||
- | < | + | |
- | CRTACT | + | |
- | VDAEMU | + | |
- | </ | + | |
- | + | ||
- | This will cause ROMWBW to check the status of BIT 6 at startup. If " | + | |
- | + | ||
- | ===== Boot " | + | |
- | + | ||
- | There is no inbuilt sound on the SBC V2 board. Complex sound output can be achieved with the ECB-SCG (Sprite-Colour-Graphics) board. | + | |
- | + | ||
- | Rudimentary sound support can be add the SBC V2 by utilizing one of the unused outputs of the RTC interfacing latch and connecting a simple amplifier to this output. | + | |
- | + | ||
- | On U18 74LS174 connect a ground wire from pin 8 and a signal wire from pin 2 to an amplifier. Generic LM386 amplifiers are available from many sources and work well. | + | |
- | + | ||
- | With this addition and the '' | + | |
- | + | ||
- | {{https:// | + | |
- | + | ||
- | ===== Speed switch modification: ===== | + | |
- | + | ||
- | The following modification allows the cpu clock speed to be changed from full to half speed under program control. The purpose of this modification is to provide a level of compatibility with MSX applications while retaining the high speed capability. Specifically a 7.159Mhz crystal can be installed for normal operation including high density floppy disk support but be switched to 3.5795Mhz to drive the Sprite Colour Graphics board when required. | + | |
- | + | ||
- | This modification requires a 74LS74 to be modified and mounted on top of U4. Five leads are required to connect to other parts of the circuit. Suggested installation method: | + | |
- | + | ||
- | Prepare connection points for new clock source: | + | |
- | + | ||
- | - Remove Z80 CPU U4 and fold out pin 6 and reinsert. | + | |
- | - Remove 74LS244 U17 and fold out pin 6 and reinsert. | + | |
- | + | ||
- | Prepare a 74LS74 for mounting on 74LS10 U4 | + | |
- | + | ||
- | - Fold up pins 1-6 and 8-13 and snip off the ends leaving the stubs. Pin 7 and 14 remain for connecting to 74LS10 U4. | + | |
- | - Solder a wire from pin 14 to pin 1 and then to pin 11 (brown wire). | + | |
- | - Solder a wire from pin 4 to pin 9 (blue wire) | + | |
- | - Solder wire from pin 13 to pin 5 (green wire) | + | |
- | - Solder wire from pin 12 to pin 7 (yellow wire) | + | |
- | + | ||
- | Mounting 74LS74 and connecting flying leads on component side of board: | + | |
- | + | ||
- | - Place the 74LS74 over 74LS10 U4 so only pin 7 and 14 are touching. | + | |
- | - Solder pin 14's together and pin 7's together. | + | |
- | - Solder a wire from pin 2 of the 74LS74 to pin 5 of 74LS174 U18 (purple wire) | + | |
- | - Solder a wire from pin 11 of the 74LS74 to pin 12 of 74LS06 U26 (orange wire) | + | |
- | - Solder a wire from pin 3 of 74LS74 to pin 13 74LS06 U26 (red wire). | + | |
- | - Solder a wire from 7 of the 74LS74 to lifted pin 6 of 74LS244 U17 and then to lifted pin 6 of Z80 CPU U24 (yellow wire) | + | |
- | + | ||
- | Solder side connections: | + | |
- | + | ||
- | - Solder wire from pin 5 of CPU clock P4 to pin 13 74LS06 U26 (red wire). | + | |
- | + | ||
- | {{https:// | + | |
- | + | ||
- | Software control | + | |
- | + | ||
- | Bit 3 of port 70h is used to select the clock speed. The normal condition is for Bit 3 to be set to 0 (low) and this will select the full clock speed of the installed crystal. Writing a 1 (high) to Bit 3 of port 70h will activate the 74LS74 clock divider. The speed switch is currently not supported in ROMWBW. Use of the RTC or speaker will reset Bit 3 to 0 i.e. full speed operation. Further, precalculated software delays or delays based on the initial speed detection at boot time do not take into account the possibility of the speed changing. | + | |
- | + | ||
- | Demonstration code: | + | |
- | + | ||
- | < | + | |
- | 1 OUT 112,0 | + | |
- | 2 PRINT " | + | |
- | 3 GOSUB 10 | + | |
- | 4 OUT 112,8 | + | |
- | 5 PRINT "SLOW SPEED" | + | |
- | 6 GOSUB 10 | + | |
- | 7 END | + | |
- | 10 FOR X=1 TO 64 | + | |
- | 20 PRINT " | + | |
- | 30 FOR Y=1 TO 256 | + | |
- | 40 NEXT Y | + | |
- | 50 NEXT X | + | |
- | 60 PRINT | + | |
- | 70 RETURN | + | |
- | </ | + | |
- | + | ||
- | + | ||
- | ===== Port Map ===== | + | |
- | + | ||
- | The SBC V2 uses address 60h - 7Fh for on board peripherals. Address decoding is not complete so some address ports are duplicated within this address range. All other I/O address ranges are exported to the ECB. | + | |
- | + | ||
- | ^Peripheral^Function^Address| | + | |
- | |82C55 PPI|Parallel Port|60h-63h ( & 64h-67h)| | + | |
- | |16550 UART|Serial Port|68h-6Fh| | + | |
- | |DS1302 RTC|Real Time Clock|70h ( & 71h-77h)| | + | |
- | |RAM|RAM bank select latch (Write Only)|78h ( & 79h)| | + | |
- | |ROM|ROM bank select latch (Write Only)|7Ch ( & 7Eh)| | + | |
\\ | \\ | ||
- | ====== Benchmark ====== | ||
- | |||
- | asciiart.bas benchmark for SBC-V2 8Mhz Z80 board running Microsoft MBASIC v5.21: | ||
- | |||
- | 2m32s | ||
- | < | ||
- | 10 FOR Y=-12 TO 12 | ||
- | 20 FOR X=-39 TO 39 | ||
- | 30 CA=X*.0458 | ||
- | 40 CB= Y*.08333 | ||
- | 50 A=CA | ||
- | 60 B=CB | ||
- | 70 FOR I=0 TO 15 | ||
- | 80 T=A*A-B*B+CA | ||
- | 90 B=2*A*B+CB | ||
- | 100 A=T | ||
- | 110 IF (A*A+B*B)> | ||
- | 120 NEXT I | ||
- | 130 PRINT " "; | ||
- | 140 GOTO 210 | ||
- | 200 IF I>9 THEN I=I+7 | ||
- | 205 PRINT CHR$(48+I); | ||
- | 210 NEXT X | ||
- | 220 PRINT | ||
- | 230 NEXT Y | ||
- | 000000011111111111111111122222233347E7AB322222111100000000000000000000000000000 | ||
- | 000001111111111111111122222222333557BF75433222211111000000000000000000000000000 | ||
- | 000111111111111111112222222233445C | ||
- | 011111111111111111222222233444556C | ||
- | 11111111111111112222233346 D978 BCF DF9 6556F4221111110000000000000000000000 | ||
- | 111111111111122223333334469 | ||
- | 1111111111222333333334457DB | ||
- | 11111122234B744444455556A | ||
- | 122222233347BAA7AB776679 | ||
- | 2222233334567 | ||
- | 222333346679 | ||
- | 234445568 | ||
- | 864332221111111000000000000000000 | ||
- | 234445568 | ||
- | 222333346679 | ||
- | 2222233334567 | ||
- | 122222233347BAA7AB776679 | ||
- | 11111122234B744444455556A | ||
- | 1111111111222333333334457DB | ||
- | 111111111111122223333334469 | ||
- | 11111111111111112222233346 D978 BCF DF9 6556F4221111110000000000000000000000 | ||
- | 011111111111111111222222233444556C | ||
- | 000111111111111111112222222233445C | ||
- | 000001111111111111111122222222333557BF75433222211111000000000000000000000000000 | ||
- | 000000011111111111111111122222233347E7AB322222111100000000000000000000000000000 | ||
- | </ | ||
- | ===== ===== | ||
- | ====== Changes and Errata: ====== | ||
- | Information regarding V1 can be found [[: | ||
- | Information regarding V2 can be found [[: | ||